ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
tCWL
tCH
ND_CE
ND_CLE
tCLEWL
tALEWL
tCLH
tALH
ND_ALE
AWE
tWP
tDWH
tDWS
ND_DATA
In Figure 23, ND_DATA is ND_D0–D15.
Figure 23. NAND Flash Controller Interface Timing—Command Wri Cycle
tCWL
ND_CE
ND_CLE
ND_ALE
tCLEWL
tALH
tALH
tALEWL
tALEWL
tWP
tWP
tWHWL
AWE
tWC
tDWS
tDWH
tDWS
tDWH
ND_DATA
In Figure 24, ND_DATA is ND_D0–D15.
Figure 24. NAND Flash Controller Interface Timing—Address Write Cycle
Rev. C
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Page 54 of 100
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February 2010