ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Table 31. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tDANW
tHAA
Switching Characteristics
ARDY Negated Delay from AMSx Asserted1
(S + WA – 2) × tSCLK ns
ARDY Asserted Hold After AWE Negated
0.0
ns
tDDAT
tENDAT
tDO
DATA15–0 Disable After CLKOUT
6.0
6.0
ns
ns
ns
ns
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT2
Output Hold After CLKOUT2
0.0
0.3
tHO
1 S = number of programmed setup cycles, WA = number of programmed write access cycles.
2 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and AWE.
PROGRAMMED
WRITE ACCESS
2 CYCLES
ACCESS
EXTENDED
2 CYCLES
SETUP
2 CYCLES
HOLD
1 CYCLE
CLKOUT
AMSx
tDO
tHO
ABE1–0
ADDR19–1
tDO
tHO
AWE
tDANW
tHAA
ARDY
tENDAT
tDDAT
DATA 15–0
Figure 16. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Rev. C
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Page 47 of 100
|
February 2010
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