ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
DDR SDRAM/Mobile DDR SDRAM Timing
Table 33 and Figure 18/Figure 19 describe DDR
SDRAM/mobile DDR SDRAM read cycle timing.
Table 33. DDR SDRAM/Mobile DDR SDRAM Read Cycle Timing
DDR SDRAM
Min
Mobile DDR SDRAM
Parameter
Max
Min
Max
Unit
Timing Requirements
tAC
Access Window of DQ0-15 to DCK0-1
–1.25
–1.25
+1.25
+1.25
0.90
0.0
0.0
6.00
6.00
0.85
ns
ns
ns
tDQSCK
tDQSQ
Access Window of DQS0-1 to DCK0-1
DQS0-1 to DQ0-15 Skew, DQS0-1 to Last
DQ0-15 Valid
tQH
DQ0-15 to DQS0-1 Hold, DQS0-1 to First
DQ0-15 to Go Invalid
tCK/2 – 1.251
tCK/2 – 1.752
0.9
tCK/2 – 1.25
ns
tRPRE
tRPST
DQS0-1 Read Preamble
DQS0-1 Read Postamble
1.1
0.6
0.9
0.4
1.1
0.6
tCK
tCK
0.4
1 For 7.50 ns ≤ tCK < 10 ns.
2 For tCK ≥ 10 ns.
t
DQSCK
DCK0-1
t
AC
DQS0-1
DQ0-15
t
t
RPST
RPRE
Dn
Dn+1
Dn+2
Dn+3
t
DQSQ
t
QH
Figure 18. DDR SDRAM Controller Read Cycle Timing
t
DQSCK
DCK0-1
t
AC
t
t
RPST
RPRE
DQS0-1
DQ0-15
Dn
Dn+1
Dn+2
Dn+3
t
DQSQ
t
QH
Figure 19. Mobile DDR SDRAM Controller Read Cycle Timing
Rev. C
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Page 49 of 100
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February 2010
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