ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Table 29. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
tHDAT
tDANR
tHAA
DATA15–0 Setup Before CLKOUT
5.0
0.8
ns
ns
DATA15–0 Hold After CLKOUT
ARDY Negated Delay from AMSx Asserted1
(S + RA – 2) × tSCLK ns
ARDY Asserted Hold After ARE Negated
0.0
0.3
ns
Switching Characteristics
tDO
Output Delay After CLKOUT2
Output Hold After CLKOUT2
6.0
ns
ns
tHO
1 S = number of programmed setup cycles, RA = number of programmed read access cycles.
2 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and ARE.
SETUP
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
2 CYCLES
1 CYCLE
CLKOUT
AMSx
tDO
tHO
ABE1–0
ADDR19–1
AOE
ARE
tDO
tHO
tDANR
tHAA
ARDY
tSDAT
tHDAT
DATA 15–0
Figure 14. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Rev. C
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Page 45 of 100
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February 2010
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