ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Asynchronous Memory Read Cycle Timing
Table 28 and Table 29 on Page 45 and Figure 13 and Figure 14
on Page 45 describe asynchronous memory read cycle opera-
tions for synchronous and for asynchronous ARDY.
Table 28. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
5.0
0.8
5.0
0.0
ns
ns
ns
ns
tHDAT
tSARDY
tHARDY
DATA15–0 Hold After CLKOUT
ARDY Setup Before the Falling Edge of CLKOUT
ARDY Hold After the Falling Edge of CLKOUT
Switching Characteristics
tDO
Output Delay After CLKOUT1
Output Hold After CLKOUT1
6.0
ns
ns
tHO
0.3
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and ARE.
SETUP
PROGRAMMED READ
ACCESS EXTENDED
3 CYCLES
HOLD
2 CYCLES
ACCESS 4 CYCLES
1 CYCLE
CLKOUT
AMSx
tDO
tHO
ABE1–0
ADDR19–1
AOE
ARE
tDO
tHO
tHARDY
tSARDY
tHARDY
ARDY
tSARDY
tSDAT
tHDAT
DATA 15–0
Figure 13. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Rev. C
|
Page 44 of 100
|
February 2010
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