AD652
adjustment is then accomplished using a 500
Ω
series trimmer.
See Figures 10a and 10b. When negative input voltages are
used, this 500
Ω
trimmer will be tied to ground and Pin 6 will
be the input pin.
This gain trim should be done with an input voltage of 9 V, and
the output frequency should be adjusted to exactly 45% of the
clock frequency. Since the device settles into a divide-by-two
mode for an input overrange condition, adjusting the gain with a
10 V input is impractical; the output frequency would be exactly
one-half the clock frequency if the gain were too high and would
not change with adjustment until the exact proper scale factor
was achieved. Hence, the gain adjustment should be done with a
9 V input.
The offset of the op amp may be trimmed to zero with the trim
scheme shown in Figures 10a for the cerdip packaged device and
Figure 10b for the PLCC packaged device. One way of trim-
ming the offset is by grounding Pin 7 (8) of the cerdip (PLCC)
packaged device and observing the waveform at Pin 4. If the off-
set voltage of the op amp is positive, then the integrator will have
saturated and the voltage will be at the positive rail. If the offset
voltage is negative, then there will be a small effective input current
that will cause the AD652 to oscillate and a sawtooth waveform
will be observed at Pin 4. The trimpot should be adjusted until
the downward slope of this sawtooth becomes very slow, down
to a frequency of 1 Hz or less. In an analog-to-digital conversion
application, an easier way to trim the offset is to apply a small
input voltage, such as 0.01% of the full-scale voltage, and adjust
the trimpot until the correct digital output is reached.
GAIN PERFORMANCE
reference voltage. For example, a 10 mA load interacting with
a 0.3
Ω
typical output impedance will change the reference
voltage by 0.06%.
DIGITAL INTERFACING CONSIDERATIONS
The AD652 clock input is a high impedance input with a
threshold voltage of two diode voltages with respect to Digital
Ground at Pin 12 (approximately 1.2 volts at room temp).
When the clock input is low, 5
µA–10 µA
flows out of this pin.
When the clock input is high, no current flows.
The frequency output is an open collector pull-down and is
capable of sinking 10 mA with a maximum voltage of 0.4 volts.
This will drive 6 standard TTL inputs. The open collector pull
up voltage can be as high as 36 volts above digital ground.
COMPONENT SELECTION
The AD652 integrating capacitor should be 0.02
µF.
If a large
amount of normal mode interference is expected (more than
0.1 volts) and the clock frequency is less than 500 kHz, an inte-
grating capacitor of 0.1
µF
should be used. Mylar, polypropylene,
or polystyrene capacitors should be used.
The open collector pull-up resistor should be chosen to give
adequately fast rise times. At low clock frequencies (100 kHz)
larger resistor values (several kΩ) and slower rise times may be
tolerated. However, at higher clock frequencies (1 MHz) a lower
value resistor should be used. The loading of the logic input
which is being driven must also be taken into consideration.
For example, if 2 standard TTL loads are to be driven then a
3.2 mA current must be sunk, leaving 6.8 mA for the pull-up
resistor if the maximum low level voltage is to be maintained at
0.4 volts. A 680
Ω
resistor would thus be selected ((5 V–0.4)V/
6.8 mA) = 680
Ω.
The one-shot capacitor controls the pulse width of the fre-
quency output. The pulse is initiated by the rising edge of the
clock signal. The delay time between the rising edge of the clock
and the falling edge of the frequency output is typically 200 ns.
The width of the pulse is 5 ns/pF and the minimum width is
about 200 ns with Pin 9 floating. If the one-shot period is acci-
dentally chosen longer than the clock period, the width of the
pulse will default to equal the clock period. The one-shot can be
disabled by connecting Pin 9 to +V
S
(Figure 12); the output
pulse width will then be equal to the clock period. The one-shot
is activated (Figure 13) by connecting a capacitor from Pin 9 to
+V
S
, –V
S
, or Digital Ground (+V
S
is preferred).
The AD652 gain error is specified as the difference in slope
between the actual and the ideal transfer function over the full-
scale frequency range. Figure 11 shows a plot of the typical
gain error changes vs. the clock input frequency, normalized
to 100 kHz. If after using the AD652 with a full-scale clock
frequency of 100 kHz it is decided to reduce the necessary gat-
ing time by increasing the clock frequency, this plot shows the
typical gain changes normalized to the original 100 kHz gain.
Figure 11. Gain vs. Clock lnput
REFERENCE NOISE
The AD652 has on board a precision buffered 5 V reference
which is available to the user. Besides being used to offset the
noninverting comparator input in the voltage-to-frequency
mode, this reference can be used for other applications such as
offsetting the input to handle bipolar signals and providing
bridge excitation. It can source 10 mA and sink 100
µA,
and is
short circuit protected. Heavy loading of the reference will not
change the gain of the VFC, although it will affect the external
–8–
Figure 12. One Shot
Disabled
Figure 13. One Shot
Enabled
REV. B
AD [ ANALOG DEVICES ]
