AD652
Figure 21. SVFC Multiplexer
Figure 22. RS-422 Standard Data Transmission
the output with an external transistor. The width of this sync
pulse is shorter than the width of the frequency output pulses to
facilitate decoding the signal. The RC lag network on the input
of the one-shot provides a slight delay between the rising edge
of the clock and the sync pulse in order to match the 150 ns
delay of the AD652 between the rising edge of the clock and
the output pulse.
Transmitter
The multiplex signal can be transmitted in any manner suitable
to the task at hand. A pulse transformer or an opto-isolator can
provide galvanic isolation; extremely high voltage isolation or
transmission through severe RF environments can be accom-
plished with a fiber-optic link; telemetry can be accomplished
with a radio link. The circuit shown in Figure 22 uses an EIA
RS-422 standard for digital data transmission over a balanced
line. Figure 24 shows the waveforms of the four clock phases
and the multiplex output signal. Note that the sync pulse is
present every clock cycle, but the data pulses are no more fre-
quent than every other clock cycle since the maximum output
frequency from the SVFC is half the clock frequency. The clock
frequency used in this circuit is 819.2 kHz and will provide
more than 16 bits of resolution if 100 millisecond gate time is
allowed for counting pulses of the decoded output frequencies.
REV. B
–12–
AD [ ANALOG DEVICES ]
