W89C840F
13:8
R/W
BL
Burst Length
BL defines the maximum number of the long words that can be
transferred within one PCI burst transaction.
The burst length configuration is as following.
[13:8] Burst Length
---------------------------------------------
00H
01H
02H
04H
08H
10H
20H
other
refer to CA
1 long word
2 long word
4 long word
8 long word
16 long word
32 long word
reserved
7
R/W
R/W
BBE
Buffer With Big Endian
When set, the data buffers are treated with big endian ordering.
When reset, the data buffers are treated with little endian
ordering.
6:2
SKIP
Skip Length Between Descriptors
This field specifies the skip length between two descriptors (from
the start address of the current descriptor to the start address of
the next descriptor). The unit of the skip length is long word.
The default value after hardware or software reset is 04H.
1
0
R/W
R/W
ARB
SWR
Arbitration Between Tx And Rx Processes
When set, the TX process and RX process will have the right to
use the internal bus with the same priority. When reset, the RX
process will have higher priority than TX process with regarding
to the internal bus utilization.
Software Reset.
Set SWR to high will reset most internal registers (except that
C38, C3c, C40, C44, C48, and PCI Configuration Registers).
The software reset will be lasted for 4 PCI clocks and the bit will
self-clean after software reset completed. If any consequent
access to the W89C840F is coming during this reset process, the
W89C840F will delay asserting TRDY# until the reset process is
completed. This bit is default 0 after hardware reset.
- 36 -
ETC [ ETC ]
