W89C840F
7
R/W
RBU
Receive Buffer Unavailable.
When there is no receive buffer available, this bit is set and the
receive process enters the suspend state.
When W89C840F is first initialized, this bit will not be set even if
there is no buffer available. It i s set only when there has been any
available buffer and no available buffer afterwards.
The RBU will not accumulate the number of the receive buffer
unavailable event, i.e. the write an 1‘ s value to RBU will clear the
RBU no matter how many times the receive buffer unavailable has
been occurred before the RBU is cleared.
6
5
R/W
R/W
RINI
IUF
Receive Interrupt
A high indicates that a frame has been received and the receive
status is transferred into the receive descriptors of the current frame.
Transmit FIFO Under-flow
A high indicates that the transmit FIFO had an under-flow error
during the packet transmission.
After the FIFO under-flow occurred, the transmit DMA will not
continue to fetch the un-transmitted data of the current frame but
fetch the descriptor of the current frame for looking for the last
descriptor of the current frame. The W89C840F‘ s transmit DMA
state machine will write the transmit status to the last descriptor of
the current frame with a 1’ s value for the bit 1 of Transmit
Descriptor 0 (T00[1]).
The W89C840F will continue to transmit next packet when the
current frame transmit status is updated..
4
R/W
RERR
Receive Error.
A high indicates that the receive DMA detects a receive error
during the packet reception.
The receive DMA will set this bit when some prior received data of
the current incoming packet have been moved into the data buffer in
the host memory and some kind of error occurred when receiving
the posterior data of the current incoming packet from the MII bus.
The INTAB i s asserted when a receive error is detected and the
receive error interrupt enable is unmasked, the error packet will be
aborted.
3
R/W
REI
Receive Early Interrupt
The REI i s set when the number of the data of the incoming frame,
in long word unit, transferred to the data buffer reaches Receive
Early Interrupt Threshold specified by the register C18/CNCR if
Receive Early Interrupt On in the register C18/CNCR is set.
This bit i s cleared automatically after Receive Interrupt (RINI) or
Receive Error (RERR) is set..
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ETC [ ETC ]
