W89C840F
C10/CTDLA Transmit Descriptors List Addresses
The registers C10/ CTDLA def i ne the start address of the transmit descriptor list. It should be updated only
when the transmission DMA state machine is staying at the stop state.
Bit
Attribute
R/W
Bit name
STL
Description
31:2
1:0
Start of Transmit List.
R/W
MBZ
Must be written as 0 for long word alignment.
C14/CISR Interrupt Status Register
Most bits of the C14/CISR report the interrupt status. The assertion of the interrupt status, reported by bits
0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 11 and 13, and the corresponding interrupt mask bits will cause a hardware
interrupt to the host.
A write with 1‘ s value the status bit will clear them and write 0 will have no effect.
Bit
Attribute
Bit name
---
Description
31:26
25:23
R
R
Reserved. Fixed at 0.
Bus Error Type.
BET
Thi s field indicates the error type of bus error, and is valid only
when bit 13, a bus error, is set.
the assertion of these bits does not generate interrupt.
The definition of bus error is as follows.
BET[25:23]
---------------
000
Error State
------------------
Parity Error
Master Abort
Target Abort
Reserved.
001
010
011
1xx
Reserved.
The meaning of the error type is described as following.
* Parity Error
--- When W89C840F operates as a bus master, it can detect a data
parity error during a read transaction or sample PERRB asserted on
a write transaction if Parity Error Response bit (F04[6]) is set.
* Master Abort
--- When W89C840F operates as a bus master, i t terminates the
read or write transaction with master abort.
* Target Abort
--- When W89C840F operates as a bus master, the read or write
transaction is terminated with target abort.
The initial state of this field after reset is zero.
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ETC [ ETC ]
