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W89C840F 参数 Datasheet PDF下载

W89C840F图片预览
型号: W89C840F
PDF下载: 下载PDF文件 查看货源
内容描述: 局域网节点控制器\n [LAN NODE CONTROLLER ]
分类和应用: 控制器局域网
文件页数/大小: 72 页 / 708 K
品牌: ETC [ ETC ]
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W89C840F  
22:20  
19:17  
16  
R
R
R
TPS  
RPS  
NIR  
Transmit Process State.  
This field indicates the transmit state. This field does not generate  
interrupt.  
Receive Process State.  
This field indicates the receive state. This field does not generate  
interrupt.  
Normal Interrupt Report.  
The normal interrupt report includes transmit completed interrupt,  
transmit buffer unavailable interrupt and the receive completed  
interrupt.  
The NIR is a logical OR result of the bits 0, 2, 6 of the register  
C14/CISR. Only the bits corresponding to the unmasked bits of  
C1C/CIMR will affect this bit.  
15  
R
AIR  
Abnormal Interrupt Report.  
The abnormal interrupt includes transmit process in idle state  
interrupt, receive early interrupt, receive error interrupt, transmit  
FIFO under-flow interrupt, receive buffer unavailable interrupt,  
receive idle state interrupt, transmit early interrupt, timer expire  
interrupt and the bus error interrupt.  
The AIR is a logical OR result of the bits 1, 3, 4, 5, 7, 8, 10, 11, 13  
of the register C14/CISR. Only these bits corresponding to the  
unmasked bits of the C1C/CIMR will affect this bit.  
14  
13  
R
---  
Reserved. Fixed at 0.  
Bus Error.  
R/W  
BE  
A high indicates a bus error happened. The error type i s shown by  
bit 25~23.  
12  
11  
R
---  
Reserved. Fixed at 0.  
R/W  
TE  
Timer Expired.  
A high indicates the general timer (C2C/CGTR) expired.  
Transmit Early Interrupt  
10  
R/W  
TEI  
The W89C840F will has Transmit Early Interrupt status set after  
the packet to be transmitted is completely transferred into the  
transmit FIFO if Transmit Early Interrupt On bit of C18/CNCR is  
set.  
The TEI i s cleared automatically after the packet is transmitted out  
from the transmit FIFO completely.  
9
8
R
---  
Reserved. Fixed at 0.  
R/W  
RIDLE  
Receive in Idle State.  
Set means the receive DMA state machine is in the idle state.  
Publication Release Date:April 1997  
- 39 -  
Revision A1  
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