W89C840F
The following table detailedly described the function of each bit of the register C00/CBCR.
Bit
Attribute
R
Bit name
---
Description
31:22
21
Reserved. Fixed at 0.
Wait State Insertion
R/W
WAIT
When as a bus mast er and WAI T ar e set , W89C840F
executes memory read/write with one wait state every data phase.
When as a bus mast er and WAI T ar e r eset , W89C840F
executes memory read/write with zero wait state every data
phase.
20
R/W
DBE
Descriptor Big Endian Mode
When set, the descriptors will be handled in big endian mode;
when reset, the descriptors will be treated in little endian mode
19:16
15:14
R
---
Reserved. Fixed at 0.
Cache Alignment
R/W
CA
CA defines the address boundary for the bur st access t o t he
t r ansmi t t ed or received data.
When the starting address of the data burst access is not aligned,
more specifically, the starting address should be a multiple of
some number such as 4, 8 etc., the W89C840F will have the first
burst transfer that causes that the next burst access will has the
start address aligned.
After the first burst occurred, all other burst operations are
aligned with the configuration of CA accordingly.
The CA must be initialized with a non zero value after reset.
The alignment configuration is as following:
[15:14]
Address Alignment
-----------------------------------------------------
[00]
[01]
[10]
[11]
reserved
8 long-word alignment
16 long-word alignment
32 long-word alignment
Publication Release Date:April 1997
Revision A1
- 35 -
ETC [ ETC ]
