W89C840F
C08
C0C
C10
CRSDR
CRDLA
CTDLA
CISR
Receive Start Demand
08H
0CH
10H
14H
18H
1CH
20H
24H
28H
2CH
30H
34H
38H
3CH
40H
44H
48H
4cH
Receive Descriptor List Address
Transmit Descriptor List Address
Interrupt Status
C14
C18
CNCR
Network Configuration
Interrupt Mask
C1C
C20
CIMR
CFDCR
CMIIR
CBROA
CGTP
Frame Discarded Counter
MII Management and ROM
Boot ROM Offset Address
General Timer
C24
C28
C2C
C30
CRDAR
CRBAR
CMA0
CMA1
CPA0
Current Receive Descriptor Address
Current Receive Buffer Address
Multicast Address 0
C34
C38
C3C
C40
Multicast Address 1
Physical Address 0
C44
CPA1
Physical Address 1
C48
CBRCR
CTDAR
CTBAR
reserved
Boot ROM Size Configuration
Current Transmit Descriptor Address
Current Transmit Buffer Address
reserved
C4c
C50
50H
reserved
C54~CFF
This table lists the initial state of each register in the W89C840F after hardware reset and software
reset separately.
Code
C00
Abbr.
hardware reset
00000010H
00000000H
00000000H
00000000H
00000000H
03800000H
20000030H
00000000H
00000000H
00000000H
software reset
00000010H
00000000H
00000000H
00000000H
00000000H
03800000H
20000030H
00000000H
00000000H
00000000H
CBCR
CTSDR
CRSDR
CRDLA
CTDLA
CISR
C04
C08
C0C
C10
C14
C18
C1C
C20
C24
CNCR
CIMR
CFDCR
CMIIR
Publication Release Date:April 1997
Revision A1
- 33 -
ETC [ ETC ]
