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OX9162 参数 Datasheet PDF下载

OX9162图片预览
型号: OX9162
PDF下载: 下载PDF文件 查看货源
内容描述: 集成并行端口/本地总线和PCI接口 [Integrated Parallel Port/Local Bus and PCI interface]
分类和应用: PC
文件页数/大小: 41 页 / 514 K
品牌: OXFORD [ OXFORD SEMICONDUCTOR ]
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OX9162  
OXFORD SEMICONDUCTOR LTD.  
4.4.5 Global Interrupt Status and Control Register ‘GIS’ (Offset 0x10)  
Bits  
Description  
Read/Write  
EEPROM  
Reset  
PCI  
1:0  
2
Reserved  
-
-
R
R
0x0h  
X
MIO0 This bit reflects the state of the internal MIO[0]. The internal MIO[0]  
reflects the non-inverted or inverted state of MIO0 pin.  
MIO1 This bit reflects the state of the internal MIO[0]. The internal MIO[0]  
reflects the non-inverted or inverted state of MIO0 pin.  
Reserved  
3
-
R
X
17-4  
18  
-
W
R
RW  
0
MIO0 INTA enable  
1 for local bus  
mode  
When set (1) allows MIO0 to assert a PCI interrupt on the INTA line. State of  
MIO0 that causes an interrupt is dependant upon the polarity set by MIC(1:0)  
0 for parallel port  
19  
MIO1 INTA enable  
W
RW  
1 for local bus  
mode  
When set (1) allows MIO1 to assert a PCI interrupt on the INTA line. State of  
MIO1 that causes an interrupt is dependant upon the polarity set by MIC(3:2)  
0 for parallel port  
20  
21  
Power-down Interrupt This is a sticky bit. When set, it indicates a power-down  
request issued and would normally have asserted a PCI interrupt if bit 21 was  
set (see section 7.9). Reading this bit clears it.  
Power-down interrupt enable. When ‘1’ a power down request is allowed to  
generate an interrupt.  
-
R
X
0
W
RW  
22  
23  
Parallel Port Mode only : Parallel port interrupt status  
Parallel Port Mode only : Parallel port interrupt enable  
-
W
R
RW  
0
1 for parallel port  
mode  
0 for local bus  
31:24 Reserved  
-
R
000h  
Data Sheet Revision 1.1 PRELIMINARY  
Page 16  
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