VT82C686B
I/O Offset 33-30 - Primary Activity Detect Status.......RWC
I/O Offset 37-34 - Primary Activity Detect Enable........ RW
These bits correspond to the Primary Activity Detect Enable
bits in offset 37-34. All bits default to 0, are set by hardware
only, and may only be cleared by writing 1s to the desired bit.
These bits correspond to the Primary Activity Detect Status
bits in offset 33-30. Setting of any of these bits also sets the
PACT_STS bit (bit-0 of offset 28) which causes the GP0 timer
to be reloaded (if PACT_GP0_EN is set) or generates an SMI
(if PACT_EN is set).
..........................................always read 0
10 Audio Access Status .............................. (AUD_STS)
......................................... always read 0
31-11 Reserved
10 SMI on Audio Status.............................. (KBC_EN)
31-11 Reserved
Set if Audio is accessed.
0
Don't set PACT_STS if AUD_STS is set ....def
1
Set PACT_STS if AUD_STS is set
9
8
7
6
5
4
3
2
1
Keyboard Controller Access Status..... (KBC_STS)
Set if the KBC is accessed via I/O port 60h.
9
8
7
6
5
4
3
2
1
SMI on Keyboard Controller Status..... (KBC_EN)
0
Don't set PACT_STS if KBC_STS is set.....def
1
Set PACT_STS if KBC_STS is set
VGA Access Status................................ (VGA_STS)
Set if the VGA port is accessed via I/O ports 3B0-
3DFh or memory space A0000-BFFFFh.
Parallel Port Access Status.................... (LPT_STS)
Set if the parallel port is accessed via I/O ports 278-
27Fh or 378-37Fh (LPT2 or LPT1).
Serial Port B Access Status .............. (COMB_STS)
Set if the serial port is accessed via I/O ports 2F8-
2FFh or 2E8-2Efh (COM2 and COM4 respectively).
Serial Port A Access Status .............. (COMA_STS)
Set if the serial port is accessed via I/O ports 3F8-
3FFh or 3E8-3EFh (COM1 and COM3, respectively).
Floppy Access Status..............................(FDC_STS)
Set if the floppy controller is accessed via I/O ports
3F0-3F5h or 3F7h.
Secondary IDE Access Status...............(SIDE_STS)
Set if the IDE controller is accessed via I/O ports
170-177h or 376h.
Primary IDE Access Status ................. (PIDE_STS)
Set if the IDE controller is accessed via I/O ports
1F0-1F7h or 3F6h.
Primary Interrupt Activity Status......(PIRQ_STS)
Set on the occurrence of a primary interrupt (enabled
via the "Primary Interrupt Channel" register at
Function 4 PCI configuration register offset 44h).
PCI Master Access Status .................... (DRQ_STS)
Set on the occurrence of PCI master activity.
SMI on VGA Status................................ (VGA_EN)
0
Don't set PACT_STS if VGA_STS is set ....def
1
Set PACT_STS if VGA_STS is set
SMI on Parallel Port Status.................... (LPT_EN)
0
Don't set PACT_STS if LPT_STS is set......def
1
Set PACT_STS if LPT_STS is set
SMI on Serial Port B Status ...............(COMB_EN)
0
Don't set PACT_STS if COMB_STS is set.def
1
Set PACT_STS if COMB_STS is set
SMI on Serial Port A Status.............. (COMA_EN)
0
Don't set PACT_STS if COMA_STS is set.def
1
Set PACT_STS if COMA_STS is set
SMI on Floppy Status .............................(FDC_EN)
0
Don't set PACT_STS if FDC_STS is set.....def
1
Set PACT_STS if FDC_STS is set
SMI on Secondary IDE Status...............(SIDE_EN)
0
Don't set PACT_STS if SIDE_STS is set....def
1
Set PACT_STS if SIDE_STS is set
SMI on PrimaryIDE Status ...................(PIDE_EN)
0
Don't set PACT_STS if PIDE_STS is set....def
1
Set PACT_STS if PIDE_STS is set
SMI on Primary INTR Status .............. (PIRQ_EN)
0
Don't set PACT_STS if PIRQ_STS is set....def
1
Set PACT_STS if PIRQ_STS is set
0
0
SMI on PCI Master Status .................... (DRQ_EN)
0
Don't set PACT_STS if DRQ_STS is set ....def
1
Set PACT_STS if DRQ_STS is set
Note: The bits above correspond to the bits of the Primary
Activity Detect Enable register at offset 34 (see right hand
column of this page): if the corresponding bit is set in that
register, setting of the above bits will cause the PACT_STS bit
to be set (bit-0 of the Global Status register at offset 28).
Setting of PACT_STS may be set up to enable a "Primary
Activity Event": an SMI will be generated if PACT_EN is set
(bit-0 of the Global Enable register at offset 2Ah) and/or the
GP0 timer will be reloaded if the "GP0 Timer Reload on
Primary Activity" bit is set (bit-0 of the GP Timer Reload
Enable register at offset 38 on this page).
Note: Bits 2-9 above also correspond to bits of the GP Timer
Reload Enable register (see offset 38 on next page): If bits are
set in that register, setting a corresponding bit in this register
will cause the GP1 timer to be reloaded.
Revision 1.71 June 9, 2000
-96-
Power Management I/O-Space Registers
ETC [ ETC ]
