VT82C686B
System Management Bus I/O-Space Registers
The base address for these registers is defined in Rx93-90 of
the Function 4 PCI configuration registers. The System
Management Bus I/O space is enabled for access by the system
if RxD2[0] = 1.
I/O Offset 00 – SMBus Host Status...............................RWC
I/O Offset 01h – SMBus Slave Status........................... RWC
........................................ always reads 0
Failed Bus Transaction....................................RWC
........................................always reads 0
Alert Status ..................................................... RWC
7-5 Reserved
7-6 Reserved
5
4
3
2
0
1
SMBus interrupt not caused by failed bus
transaction ..............................................default
SMBus interrupt caused by failed bus
transaction. This bit may be set when the
KILL bit (I/O Rx02[1]) is set and can be
cleared by writing a 1 to this bit position.
0
1
SMBus interrupt not caused by SMBALERT#
signal .................................................... default
SMBus interrupt caused by SMBALERT#
signal. This bit will be set only if the Alert
Enable bit is set in the SMBus Slave Control
Register at I/O Offset R08[3]. This bit is only
set by hardware and can be cleared by writing
a 1 to this bit position.
Bus Collision.....................................................RWC
0
SMBus interrupt not caused by transaction
collision..................................................default
SMBus interrupt caused by transaction
collision. This bit is only set by hardware and
can be cleared by writing a 1 to this bit
position.
4
3
2
Shadow 2 Status............................................... RWC
1
0
SMBus interrupt not caused by address match
to SMBus Shadow Address Port 2......... default
SMBus interrupt or resume event caused by
slave cycle address match to SMBus Shadow
Address Port 2. This bit is only set by
hardware and can be cleared by writing a 1 to
this bit position.
1
Device Error.....................................................RWC
0
SMBus interrupt not caused by generation of
an SMBus transaction error....................default
SMBus interrupt caused by generation of an
SMBus transaction error (illegal command
field, unclaimed host-initiated cycle, or host
device timeout). This bit is only set by
hardware and can be cleared by writing a 1 to
this bit position.
1
Shadow 1 Status............................................... RWC
0
SMBus interrupt not caused by address match
to SMBus Shadow Address Port 1......... default
SMBus interrupt or resume event caused by
slave cycle address match to SMBus Shadow
Address Port 1. This bit is only set by
hardware and can be cleared by writing a 1 to
this bit position.
1
1
0
SMBus Interrupt..............................................RWC
0
SMBus interrupt not caused by host command
completion..............................................default
SMBus interrupt caused by host command
completion. This bit is only set by hardware
and can be cleared by writing a 1 to this bit
position.
Slave Status ..................................................... RWC
1
0
SMBus interrupt not caused by slave event
match .................................................... default
SMBus interrupt or resume event caused by
slave cycle event match of the SMBus Slave
1
Command Register at PCI Function
4
Host Busy ..........................................................RO
0
SMBus controller host interface is not
processing a command ...........................default
SMBus host controller is busy processing a
command. None of the other SMBus registers
should be accessed if this bit is set.
Configuration Offset D3h (command match)
and the SMBus Slave Event Register at
SMBus Base + Offset 0Ah (data event match).
This bit is only set by hardware and can be
cleared by writing a 1 to this bit position.
1
........................................always reads 0
Slave Busy ......................................................... RO
1
0
Reserved
0
1
SMBus controller slave interface is not
processing data ...................................... default
SMBus controller slave interface is busy
receiving data. None of the other SMBus
registers should be accessed if this bit is set.
Revision 1.71 June 9, 2000
-99-
System Management Bus I/O-Space Registers
ETC [ ETC ]
