VT82C686B
General Purpose Power Management Registers
I/O Offset 21-20 - General Purpose Status (GP_STS).RWC
I/O Offset 23-22 - General Purpose SCI Enable ............ RW
........................................ always reads 0
........................................always reads 0
15 Reserved
15 Reserved
def=0
def=0
14 USB Wake-Up Status (UWAK_STS)
For STR / STD / Soff
14 Enable SCI on setting of the UWAK_STS bit
13 Enable SCI on setting of the AWAK_STS bit
13 AC97 Wake-Up Status (AWAK_STS)
Can be set only in suspend mode
12 Battery Low Status (BL_STS)
This bit is set when the BATLOW# input is asserted
low.
11 Notebook Lid Status (LID_STS)
This bit is set when the LID input detects the edge
selected by Rx2C bit-7 (0=rising, 1=falling).
10 Thermal Detect Status (THRM_STS)
This bit is set when the THRM input detects the edge
selected by Rx2C bit-6 (0=rising, 1=falling).
......def=0
.....def=0
12 Enable SCI on setting of the BL_STS bit
11 Enable SCI on setting of the LID_STS bit
10 Enable SCI on setting of the THRM_STS bit
def=0
....def=0
.def=0
..def=0
9
8
7
6
5
4
3
2
1
0
Enable SCI on setting of the USB_STS bit
Enable SCI on setting of the RING_STS bit
Enable SCI on setting of the GPI18_STS bit
....def=0
....def=0
....def=0
..def=0
..def=0
Enable SCI on setting of the GPI6_STS bit
Enable SCI on setting of the GPI5_STS bit
Enable SCI on setting of the GPI4_STS bit
Enable SCI on setting of the GPI17_STS bit
Enable SCI on setting of the GPI16_STS bit
9
USB Resume Status (USB_STS)
....def=0
....def=0
Enable SCI on setting of the GPI1_STS bit
Enable SCI on setting of the EXT_STS bit
This bit is set when a USB peripheral generates a
resume event.
These bits allow generation of an SCI using a separate set of
conditions from those used for generating an SMI.
8
7
6
5
4
3
2
1
0
Ring Status (RING_STS)
This bit is set when the RING# input is asserted low.
GPI18 Toggle Status (GPI18_STS)
This bit is set when the GPI18 pin is toggled.
GPI6 / EXTSMI6 Toggle Status (GPI6_STS)
This bit is set when the GPI6 pin is toggled.
GPI5 Toggle Status (GPI5_STS)
This bit is set when the GPI5 pin is toggled.
GPI4 / EXTSMI4 Toggle Status (GPI4_STS)
This bit is set when the GPI4 pin is toggled.
GPI17 Toggle Status (GPI17_STS)
This bit is set when the GPI17 pin is toggled.
GPI16 Toggle Status (GPI16_STS)
This bit is set when the GPI16 pin is toggled.
GPI1 Toggle Status (GPI1_STS)
I/O Offset 25-24 - General Purpose SMI Enable ........... RW
........................................always reads 0
15-14 Reserved
def=0
13 Enable SMI on setting of the AWAK_STS bit
.....def=0
12 Enable SMI on setting of the BL_STS bit
11 Enable SMI on setting of the LID_STS bit
10 Enable SMI on setting of the THRM_STS bit
....def=0
def=0
...def=0
def=0
9
8
7
6
5
4
3
2
1
0
Enable SMI on setting of the USB_STS bit
Enable SMI on setting of the RING_STS bit
Enable SMI on setting of the GPI18_STS bit
.def=0
...def=0
...def=0
...def=0
.def=0
.def=0
Enable SMI on setting of the GPI6_STS bit
Enable SMI on setting of the GPI5_STS bit
Enable SMI on setting of the GPI4_STS bit
Enable SMI on setting of the GPI17_STS bit
Enable SMI on setting of the GPI16_STS bit
This bit is set when the GPI1 pin is toggled.
EXTSMI# Status (EXT_STS)
...def=0
Enable SMI on setting of the GPI1_STS bit
This bit is set when the EXTSMI# pin is asserted low.
....def=0
Enable SMI on setting of the EXT_STS bit
These bits allow generation of an SMI using a separate set of
conditions from those used for generating an SCI.
Note that the above bits correspond one for one with the bits
of the General Purpose SCI Enable and General Purpose SMI
Enable registers at offsets 22 and 24: an SCI or SMI is
generated if the corresponding bit of the General Purpose SCI
or SMI Enable registers, respectively, is set to one.
The above bits are set by hardware only and can only be
cleared by writing a one to the desired bit.
Revision 1.71 June 9, 2000
-93-
Power Management I/O-Space Registers
ETC [ ETC ]
