VT82C686B
I/O Offset 02h – SMBus Host Control.............................RW
I/O Offset 03h – SMBus Host Command........................ RW
........................................ always reads 0
........................................ always reads 0
Writing 0 has no effect...........................default
Start Execution of Command
Writing a 1 to this bit causes the SMBus
controller host interface to initiate execution of
the command programmed in the SMBus
..........................default = 0
7-0 SMBUS Host Command
7
6
Reserved
Start
This field contains the data transmitted in the
command field of the SMBus host transaction.
0
1
I/O Offset 04h – SMBus Host Address............................ RW
The contents of this register are transmitted in the address field
of the SMBus host transaction.
.......................................default = 0
7-1 SMBUS Address
Command Protocol field (bits 4-2).
All
This field contains the 7-bit address of the targeted
slave device.
SMBUS Read or Write
necessary registers should be programmed
prior to writing a 1 to this bit. The Host Busy
bit (SMBus Host Status Register bit-0) can be
used to identify when the SMBus controller
has completed command execution.
0
0
Execute a WRITE command ................. default
1
Execute a READ command
5-2 SMBus Command Protocol
0000 Quick Read or Write ..............................default
0001 Byte Read or Write
0010 Byte Data Read or Write
0011 Word Data Read or Write
0100 Process Call
I/O Offset 05h – SMBus Host Data 0 .............................. RW
The contents of this register are transmitted in the Data 0 field
of SMBus host transaction writes. On reads, Data 0 bytes are
stored here.
..........................................default = 0
7-0 SMBUS Data 0
For Block Write commands, this field is programmed
with the block transfer count (a value between 1 and
32). Counts of 0 or greater than 32 are undefined.
For Block Read commands, the count received from
the SMBus device is stored here.
0101 Block Read or Write
0110 I2C with 10-bit Address
0111 Reserved
1000 -reserved-
1001 -reserved-
1010 -reserved-
1011 -rreserved-
1100 I2C Process Call
1101 I2C Block
1110 I2C with 7-bit Address
1111 Universal
I/O Offset 06h – SMBus Host Data 1 .............................. RW
The contents of this register are transmitted in the Data 1 field
of SMBus host transaction writes. On reads, Data 1 bytes are
stored here.
..........................................default = 0
7-0 SMBUS Data 1
1
0
Kill Transaction in Progress
I/O Offset 07h – SMBus Block Data ............................... RW
0
1
Normal host controller operation ...........default
Stop host transaction currently in progress.
Setting this bit also sets the FAILED status bit
(Host Status bit-4) and asserts the interrupt
selected by the SMB Interrupt Select bit
Reads and writes to this register are used to access the 32-byte
block data storage array. An internal index pointer is used to
address the array. It is reset to 0 by reads of the SMBus Host
Control register (I/O Offset 2) and incremented automatically
by each access to this register. The transfer of block data into
(read) or out of (write) this storage array during an SMBus
transaction always starts at index address 0.
(Function
Register RxD2[3]).
Interrupt Enable
4
SMBus Host Configuration
..................................default = 0
7-0 SMBUS Block Data
0
Disable interrupt generation ...................default
1
Enable generation of interrupts on completion
of the current host transaction.
Revision 1.71 June 9, 2000
-100-
System Management Bus I/O-Space Registers
ETC [ ETC ]
