VT82C686B
Generic Power Management Registers
I/O Offset 29-28 - Global Status....................................RWC
I/O Offset 2B-2A - Global Enable ................................... RW
...... def=0
...... def=0
...... def=0
...... def=0
..........def=0
..........def=0
15 GPIO Range 1 Access Status (GR1_STS)
14 GPIO Range 0 Access Status (GR0_STS)
13 GP3 Timer Timeout Status (G3TO_STS)
12 GP2 Timer Timeout Status (G2TO_STS)
15 GPIO Range 1 SMI Enable (GR1_EN)
14 GPIO Range 0 SMI Enable (GR0_EN)
13 GP3 Timer Timeout SMI Enable (G3TO_EN)
12 GP2 Timer Timeout SMI Enable (G2TO_EN)
def=0
def=0
.................. def=0
..................def=0
11 SERIRQ SMI Enable (SSMI_EN)
.......................def=0
10 SERIRQ SMI Enable (SE_EN)
11 SERIRQ SMI Status (SSMI_STS)
. def=0
10 SLP Ena (Rx5[5]) Wr SMI Status (SE_STS)
........................................ always reads 0
........................................always reads 0
9
8
Reserved
9
8
Reserved
.... def=0
....def=0
PCKRUN# Resume Status (PRRSM_STS)
PCKRUN# Resume Enable (PRRSM_EN)
This bit is set when PCI bus peripherals wake up the
system by asserting PCKRUN#
This bit may be set to trigger an SMI to be generated
when the PRRSM_STS bit is set.
. def=0
..def=0
Primary IRQ Resume Enable (PIRSM_EN)
This bit may be set to trigger an SMI to be generated
when the PIRSM_STS bit is set.
...........def=0
SMI on Software SMI (SW_SMI_EN)
This bit may be set to trigger an SMI to be generated
when the SW_SMI_STS bit is set.
7
6
5
Primary IRQ Resume Status (PIRSM_STS)
7
6
5
This bit is set at the occurrence of primary IRQs as
defined in Rx45-44 of PCI configuration space
............ def=0
This bit is set when the SMI_CMD port (offset 2F) is
written.
Software SMI Status (SW_SMI_STS)
................................ def=0
....................def=0
SMI on BIOS Status (BIOS_EN)
BIOS Status (BIOS_STS)
This bit is set when the GBL_RLS bit is set to one
(typically by the ACPI software to release control of
the SCI/SMI lock). When this bit is reset (by writing
a one to this bit position) the GBL_RLS bit is reset at
the same time by hardware.
This bit may be set to trigger an SMI to be generated
when the BIOS_STS bit is set.
............ def=0
This bit is set when a legacy USB event occurs.
4
3
2
1
SMI on Legacy USB (LEG_USB_EN)............def=0
This bit may be set to trigger an SMI to be generated
when the LEG_USB_STS bit is set.
.def=0
SMI on GP1 Timer Time Out (GP1TO_EN)
This bit may be set to trigger an SMI to be generated
when the GP1TO_STS bit is set.
.def=0
SMI on GP0 Timer Time Out (GP0TO_EN)
This bit may be set to trigger an SMI to be generated
when the GP0TO_STS bit is set.
4
3
2
1
Legacy USB Status (LEG_USB_STS)
.. def=0
GP1 Timer Time Out Status (GP1TO_STS)
This bit is set when the GP1 timer times out.
.. def=0
GP0 Timer Time Out Status (GP0TO_STS)
This bit is set when the GP0 timer times out.
Secondary Event Timer Time Out Status
..................................................... def=0
SMI on Secondary Event Timer Time Out
(STTO_STS)
......................................................def=0
(STTO_EN)
This bit is set when the secondary event timer times
out.
This bit may be set to trigger an SMI to be generated
when the STTO_STS bit is set.
............ def=0
0
Primary Activity Status (PACT_STS)
...........def=0
SMI on Primary Activity (PACT_EN)
0
This bit is set at the occurrence of any enabled
primary system activity (see the Primary Activity
Detect Status register at offset 30h and the Primary
Activity Detect Enable register at offset 34h). After
checking this bit, software can check the status bits in
the Primary Activity Detect Status register at offset
30h to identify the specific source of the primary
event. Note that setting this bit can be enabled to
reload the GP0 timer (see bit-0 of the GP Timer
Reload Enable register at offset 38).
This bit may be set to trigger an SMI to be generated
when the PACT_STS bit is set.
Note that SMI can be generated based on the setting of any of
the above bits (see the offset 2Ah Global Enable register bit
descriptions in the right hand column of this page).
The bits in this register are set by hardware only and can only
be cleared by writing a one to the desired bit position.
Revision 1.71 June 9, 2000
-94-
Power Management I/O-Space Registers
ETC [ ETC ]
