VT82C686B
I/O Offset 3B-38 - GP Timer Reload Enable ..................RW
I/O Offset 40 – Extended I/O Trap Status................... RWC
All bits in this register default to 0 on power up.
......................................... always read 0
7-5 Reserved
..........................................always read 0
31-8 Reserved
4
BIOS Write Enable Status...................(BWR_STS)
(Function 0 Rx40[7])
7
GP1 Timer Reload on KBC Access
0
1
Normal GP1 Timer Operation................default
Setting of KBC_STS causes the GP1 timer to
reload.
......................................... always read 0
GPIO Range 3 Access Status.............. (GPR3_STS)
GPIO Range 2 Access Status.............. (GPR2_STS)
3-2 Reserved
1
0
6
GP1 Timer Reload on Serial Port Access
I/O Offset 42 – Extended I/O Trap Enable..................... RW
......................................... always read 0
SMI on BIOS Write............................... (BWR_EN)
0
Normal GP1 Timer Operation ...............default
Setting of COMA_STS or COMB_STS causes
the GP1 timer to reload.
7-5 Reserved
4
1
0
Disable................................................... default
1
Enable
..........................................always read 0
5
4
Reserved
......................................... always read 0
SMI on GPIO Range 3 Access..............(GPR3_EN)
3-2 Reserved
1
GP1 Timer Reload on VGA Access
0
1
Disable................................................... default
Enable
0
1
Normal GP1 Timer Operation ...............default
Setting of VGA_STS causes the GP1 timer to
reload.
0
SMI on GPIO Range 2 Access..............(GPR2_EN)
0
1
Disable................................................... default
Enable
3
GP1 Timer Reload on IDE/Floppy Access
0
1
Normal GP1 Timer Operation ...............default
Setting of FDC_STS, SIDE_STS, or
PIDE_STS causes the GP1 timer to reload.
2
1
GP3 Timer Reload on GPIO Range 1 Access
0
1
Normal GP3 Timer Operation ...............default
Setting of GR1_STS causes the GP3 timer to
reload.
GP2 Timer Reload on GPIO Range 0 Access
0
1
Normal GP2 Timer Operation ...............default
Setting of GR0_STS causes the GP2 timer to
reload.
0
GP0 Timer Reload on Primary Activity
0
1
Normal GP0 Timer Operation ...............default
Setting of PACT_STS causes the GP0 timer to
reload. Primary activities are enabled via the
Primary Activity Detect Enable register (offset
37-34) with status recorded in the Primary
Activity Detect Status register (offset 33-30).
Revision 1.71 June 9, 2000
-97-
Power Management I/O-Space Registers
ETC [ ETC ]
