VT82C686B
Processor Power Management Registers
I/O Offset 13-10 - Processor & PCI Bus Control............RW
I/O Offset 14 - Processor Level 2...................................... RO
........................................ always reads 0
........................................always reads 0
31-12 Reserved
7-0 Level 2
Reads from this register put the processor into the
Stop Grant state (the VT82C686B asserts STPCLK#
to suspend the processor). Wake up from Stop Grant
state is by interrupt (INTR, SMI, and SCI).
11 PCI Stop (PCISTP# asserted) when PCKRUN# is
Deasserted (PCI_STP)
0
Enable.....................................................default
1
Disable
10 PCI Bus Clock Run Without Stop (PCI_RUN)
Reads from this register return all zeros; writes to this register
have no effect.
0
PCKRUN# will be de-activated after the PCI
bus is idle for 26 clocks..........................default
PCKRUN# is always asserted
1
I/O Offset 15 - Processor Level 3...................................... RO
9
8
Host Clock Stop Enable (HOST_STP)
........................................always reads 0
7-0 Level 3
0
STPCLK# will be asserted in the C3 state, but
the CPU clock is not stopped .................default
CPU clock is stopped in the C3 state
Reads from this register put the processor in the C3
clock state with the STPCLK# signal asserted. If
Rx10[9] = 1 then the CPU clock is also stopped by
asserting CPUSTP#. Wakeup from the C3 state is by
interrupt (INTR, SMI, and SCI).
1
Assert SLP# for Processor Level 3 Read
0
Disable ...................................................default
1
Enable
Reads from this register return all zeros; writes to this register
have no effect.
Used in Slot-1 systems only.
........................................ always reads 0
7-5 Reserved
4
Throttling Enable (THT_EN)
Setting this bit starts clock throttling (modulating the
STPCLK# signal) regardless of the CPU state. The
throttling duty cycle is determined by bits 3-0 of this
register.
3-0 Throttling Duty Cycle (THT_DTY)
This 4-bit field determines the duty cycle of the
STPCLK# signal when the system is in throttling
mode (the "Throttling Enable" bit is set to one). The
duty cycle indicates the percentage of time the
STPCLK# signal is asserted while the Throttling
Enable bit is set. The field is decoded as follows:
0000 Reserved
0001 0-6.25%
0010 6.25-12.50%
0011 18.75-25.00%
0100 31.25-37.50%
0101 37.50-43.75%
0110 43.75-50.00%
0111 50.00-56.25%
1000 56.25-62.50%
1001 62.50-68.75%
1010 68.75-75.00%
1011 75.00-87.50%
1100 75.00-81.25%
1101 81.25-87.50%
1110 87.50-93.75%
1111 93.75-100%
Revision 1.71 June 9, 2000
-92-
Power Management I/O-Space Registers
ETC [ ETC ]
