VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
LP_LOW and CP_LP_HIGH are the error correction code data registers. They are modified
when DSPI_ODATA or DSPI_IDATA ports are accessed. The DSPI_CF_ECCENA must be set
in order to use ECC.
DSPI_CF Bits
Name
Bits Description
DSPI_CF_ODAT
15:12 RS_ODATA mux control
DSPI_CF_ECCRST
DSPI_CF_ECCENA
DSPI_CF_WRBUF
DSPI_CF_RDBUF
9
8
1
0
ECC reset
ECC enable
Data buffer write enable
Data buffer read enable
DSPI_CF_ODAT is a control register for RS_ODATA register.
DSPI_CF_ECCRST and DSPI_CF_ECCENA control the ECC unit. DSPI_CF_ECCRST reset
the unit when set. THe register is reset automatically after one clock cycle.
DSPI_CF_ECCENA register enables the ECC calculation. column parity (CP) and line parity
(LP) registers are modified when data is read from DSPI_ODATA or written to DSPI_IDATA
register and DSPI_CF_ECCENA is set.
DSPI_CF_WRBUF and DSPI_CF_RDBUF enable the dsp access to peripheral data buffer.
When either register is set the DSPI_ADDR is incremented on each memory access and data
is read (DSPI_ODATA) or written (DSPI_IDATA) to memory.
Data interfaces can generate only one interrupt request for the DSP. The interrupt source is
stored in interrupt status register.
DSPI_STATUS register is used to track the interrupt source of the peripherals using data buffer
memory. The interrupt requests are reset when the register bit is set by software. Interrupt
sources are listed in the table.
Version: 0.2, 2012-03-16
52
ETC [ ETC ]
