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VS1005 参数 Datasheet PDF下载

VS1005图片预览
型号: VS1005
PDF下载: 下载PDF文件 查看货源
内容描述: 此产品是芬兰VLSI刚刚研发成功的音频编解码芯片样品 [此产品是芬兰VLSI刚刚研发成功的音频编解码芯片样品]
分类和应用:
文件页数/大小: 104 页 / 1715 K
品牌: ETC [ ETC ]
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VS1005g Datasheet  
10 VS1005 PERIPHERALS AND REGISTERS  
don’t care.  
ETH_TXPNTR_BUSY is the ethernet transmitter busy flag. In SPI slave mode this flag is set if  
transmitter is enabled and chip select line is in its active state (low).  
ETH_TXPNTR_START enables the ethernet transmitter. When this register is set the transmit-  
ter changes from idle to busy state and sends ETH_TXLEN[11:0] number of bytes. Before this  
register is set the packet data must be stored in peripheral memory and tx address pointer and  
tx packet length registers must be configured. In SPI slave mode this register is zero.  
ETH_TXPNTR[10:0] is the ethernet/SPI transmitter memory address pointer. This pointer is  
loaded with packet start address before transmitter is enabled.  
ETH_RXLEN Bits  
Name  
Bits Description  
ETH_RXLEN_PMODE  
15 Peripheral mode select: Ethernet (0) / SPI  
slave mode (1)  
ETH_RXLEN_STCLK  
ETH_RXLEN[11:0]  
14 SPI slave transmitter clock configuration  
11:0 Ethernet receiver packet size in bytes  
ETH_RXLEN_PMODE register configures the peripheral to ethernet mode or to SPI slave  
mode. When register is reset (default state) the peripheral is in ethernet mode.  
ETH_RXLEN_STCLK selects SPI slave transmitter clock edge. When register is reset the SPI  
out data is written after falling SPI clock edge. When register is set the data is written after  
rise edge. With high SPI bit rates (SPI clock > core clock / 6) the rise edge should be used. It  
should be noted that the SPI slave clock can not exceed core clock / 4 at any time. In ethernet  
mode this register is don’t care.  
ETH_RXLEN[11:0] register is loaded with ethernet/SPI receiver packet length counter when  
receiver returns from busy state to idle (packet end). Packet length is given in bytes.  
ETH_RXPNTR Bits  
Name  
Bits Description  
ETH_RXPNTR_CRCOK  
ETH_RXPNTR_NEWPKT  
ETH_RXPNTR_BUSY  
ETH_RXPNTR_ENA  
ETH_RXPNTR[10:0]  
15 Ethernet receiver crc status flag  
14 Ethernet receiver packet received flag  
13 Ethernet receiver busy  
12 Ethernet receiver enable  
10:0 Ethernet receiver memory address pointer  
ETH_RXPNTR_CRCOK is the received packet crc status flag. Receiver sets the flag if the  
received packet crc was correct. Flag must be reset by user (write ’1’). In SPI slave mode the  
crc flag is set if last four bytes were 0xFF.  
ETH_RXPNTR_NEWPKT is the flag for incoming packet. The receiver sets the flag when it  
changes its state from busy to idle. Flag must be reset by user (write ’1’). In spi mode this  
register is zero.  
ETH_RXPNTR_BUSY is a busy flag for ethernet/SPI slave receiver. This receiver sets the flag  
when changes its state from idle to busy state.  
ETH_RXPNTR_ENA register places the ethernet receiver on hold for incoming packet when  
set. When packet start is detected the receiver switches from idle to busy state. Receiver  
Version: 0.2, 2012-03-16  
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