VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
Status SPIx_STATUS Bits
Bits Description
Name
SPI_ST_RXFIFOFULL
SPI_ST_TXFIFOFULL
7
6
Receiver FIFO register full
Transmitter FIFO register full
SPI_ST_BREAK
5
4
3
2
1
0
Chip select deasserted mid-transfer
Receiver overrun
Receiver data register full
Transmitter data register full
Transmitter running
SPI_ST_RXORUN
SPI_ST_RXFULL
SPI_ST_TXFULL
SPI_ST_TXRUNNING
SPI_ST_TXURUN
Transmitter underrun
SPI_ST_BREAK is set in slave mode if chip select was deasserted in interrupted xCS mode or
a starting edge is encountered in xCS edge modes while a data transfer was in progress. This
bit has to be cleared manually.
SPI_ST_RXORUN is set if a received byte overwrites unread data when it is transferred from
the receiver shift register to the data register. This bit has to be cleared manually.
SPI_ST_RXFULL is set if there is unread data in the data register.
SPI_ST_TXFULL is set if the transmit data register is full.
SPI_ST_TXRUNNING is set if the transmitter shift register is in operation.
SPI_ST_TXURUN is set if an external data transfer has been initiated in slave mode and the
transmit data register has not been loaded with new data to shift out. This bit has to be cleared
manually.
Note: Because TX and RX status bits are implemented as separate entities, it is relatively easy
to make asynchronous software implementations, which do not have to wait for an SPI cycle to
finish.
SPIx_DATA[SPI_CF_DLEN:0] may be written to whenever SPI_ST_TXFULL is clear. In master
mode, writing will initiate an SPI transaction cycle of SPI_CF_DLEN+1 bits. In slave mode,
data is output as soon as suitable external clocks are offered. Writing to SPI_DATA sets
SPI_ST_TXFULL, which will again be cleared when the data word was put to the shift reg-
ister. If SPI_ST_TXRUNNING was clear when SPI_DATA was written to, data can immediately
be transferred to the shift register and SPI_ST_TXFULL won’t be set at all.
When SPI_ST_RXFULL is set, SPI_DATA may be read. Bits SPI_CF_DLEN:0 contain the
received data. The rest of the 16 register bits are set to 0.
SPIx_FSYNC is meant for generation of potentially complex synchronization signals, including
several SSI variants as well as a simple enough automatic chip select signal. SPIx_FSYNC is
only valid in master mode.
If a write to SPIx_DATA is preceded by a write to SPIx_FSYNC, the data written to SPIx_FSYNC
is sent to FSYNC pin with the same synchronization as the data written to SPIx_DATA is written
to MOSI. When SPI_ST_TXRUNNING is clear, the value of SPI_CF_FSIDLE is set to FSYNC
pin.
If SPIx_DATA is written to without priorly writing to SPIx_FSYNC, the last value written to
SPIx_FSYNC is sent.
Version: 0.2, 2012-03-16
49
ETC [ ETC ]
