VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
DSPI_STATUS Bits
Bits Description
Name
DSPI_ST_IENA
14 Interrupt enable for data buffer peripherals
13 Ethernet transmit ring buffer full
12 Ethernet transmit ring buffer half full
11 Ethernet receive ring buffer emptyl
10 Ethernet receive ring buffer half empty
DSPI_ST_ETRB1
DSPI_ST_ETRB0
DSPI_ST_ERRB1
DSPI_ST_ERRB0
DSPI_ST_SPIERR
9
SPI slave error, transfer was interrupted mid-
dle of byte
DSPI_ST_BMCSF
8
Reed-Solomon decode error correction data
ready
DSPI_ST_RSDEC
DSPI_ST_RSENC
DSPI_ST_SD
DSPI_ST_NF
DSPI_ST_SPISTP
7
6
5
4
3
Reed-Solomon decode ready
Reed-Solomon encode ready
SD card interface ready interrupt
Nand flash interface ready interrupt
SPI slave stop interrupt, chip select to inactive
state
DSPI_ST_SPISTR
2
SPI slave start interrupt, chip select to active
state
DSPI_ST_ETHRX
DSPI_ST_ETHTX
1
0
Ethernet receiver new packet interrupt
Ethernet transmitter ready interrupt
DSPI_ST_IENA is the peripheral interrupt enable. When set the interrupt requests are for-
warded to interrupt controller. Interrupt requests in DSPI_STATUS register are modified re-
gardless the value of DSPI_ST_IENA.
The SPI slave error register (DSPI_ST_SPIERR) is a read only register which is reset when
SPI start is detected in the SPI bus and set if data transfer was interrupted in the middle of a
byte.
Version: 0.2, 2012-03-16
53
ETC [ ETC ]
