VS1005g Datasheet
10
10.10.1 Ethernet Controller
VS1005 PERIPHERALS AND REGISTERS
Reg
0xFC60
0xFC61
0xFC62
0xFC63
0xFC64
0xFC65
Type
r/w
r/w
r/w
r/w
r/w
r
Reset
0
0
0
0
0
0
Ethernet Controller Registers
Abbrev
Description
ETH_TXLEN
Ethernet transmitter packet length
ETH_TXPNTR Ethernet transmitter memory address pointer
ETH_RXLEN
Ethernet receiver packet length
ETH_RXPNTR Ethernet receiver memory address pointer
ETH_RBUF
Ethernet transmitter/receiver ring buffer configuration
ETH_RXADDR Ethernet receiver memory address, 11 bits
ETH_TXLEN Bits
Bits Description
15 SPI slave synhronization configuration
14 SPI slave receiver bit order
13 SPI slave transmitter bit order
11:0 Ethernet transmitter packet size in bytes
Name
ETH_TXLEN_META
ETH_TXLEN_RBO
ETH_TXLEN_TBO
ETH_TXLEN[11:0]
PR
EL
IM
Name
ETH_TXPNTR_SPITE
ETH_TXPNTR_SPIRE
ETH_TXPNTR_BUSY
ETH_TXPNTR_START
ETH_TXPNTR[10:0]
Version: 0.2, 2012-03-16
ETH_TXLEN_META register enables the use of higher bit rate. If the SPI slave and master are
using same clock source this register can be set. The SPI slave synchronization is then made
simpler. It is recommended to keep this register in reset. In ethernet mode this register is don’t
care.
ETH_TXLEN_RBO and ETH_TXLEN_TBO are used to reverse bit order. When registers are
reset the bits are sent/received lsb bit first (i.e. from 0 to 7). When registers are set the bits are
sent/received msb bit first (i.e. from 7 to 0). In ethernet mode these registers are don’t care.
ETH_TXLEN[11:0] register is loaded with packet length (in bytes) before the transmitter is en-
abled. When transmitter is enabled this register is decremented after a byte has been sent.
When the length register reached zero the transmitter returns to idle state. In SPI slave mode
this register is zero.
ETH_TXPNTR Bits
Bits Description
15 SPI slave transmitter enable
14 SPI slave receiver enable
13 Ethernet transmitter busy
12 Ethernet transmitter start-to-send packet
10:0 Ethernet transmitter memory address pointer
ETH_TXPNTR_SPITE and ETH_TXPNTR_SPIRE are the SPI slave mode enables for trans-
mitter and receiver. SPI start and stop interrupts are generated even though these registers
would be reset. It should be noted that when ETH_TXPNTR_SPIRE is set the transmitter ad-
dress pointer must be initialized to data start address. In ethernet mode these registers are
54
IN
AR
Vs1005 has a controller for interfacing 10base-t ethernet bus. Additionally this peripheral can
be configured to SPI slave mode to be used with VLSI Solution’s RF link. In this mode the SPI1
pins are used and they must be configured to peripheral mode with GPMODE1[7:4] registers.
Y
ETC [ ETC ]
