VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
address pointer must be configured before this register is set. In SPI slave mode this regis-
ter controls the SPI receiver enable. When register is set the SPI transmit end automatically
enables the SPI receiver.
ETH_RXPNTR[10:0] is the ethernet/SPI receiver memory pointer. This pointer is loaded with
packet start address before receiver is enabled. When receiver changes it state from idle to
busy this register is loaded to memory write address pointer register.
ETH_RBUF Bits
Name
Bits Description
ETH_RBUF_CKCFG
ETH_RBUF_TXENA
ETH_RBUF_TXCFG
ETH_RBUF_RXENA
ETH_RBUF_RXCFG
9:8 Reserved, use “00”
7
Ethernet receiver ring buffer enable
6:4 Ethernet receiver ring buffer configuration
3
Ethernet transmitter ring buffer enable
2:0 Ethernet transmitter ring buffer configuration
ETH_RBUF_TXENA and ETH_RBUF_RXENA are ring buffer enable registers for transmitters
and receiver respectively. Ring buffer size is defined with ETH_RBUF_TXCFG and ETH_RBUF_RXCFG
registers as explained in next table.
Ring buffer configuration bits
CFG register Ring buffer size Locked bits Incremented bits
111-100
011
1024 words
512 words
256 words
128 words
64 words
[10]
[10:9]
[10:8]
[10:7]
[10:6]
[9:0]
[8:0]
[7:0]
[6:0]
[5:0]
010
001
000
ETH_RXADDR register is the current memory address were receiver stores data. This register
is loaded with ETH_RXPNTR[10:0] when new packet start is detected in bus.
Ethernet controller generates an interrupt each time a new packet is received or transmitter
has finished sending a packet. When ring buffers are used the interrupt is given also when ring
buffer address pointer has reached middle or end of the configured buffer size.
Version: 0.2, 2012-03-16
56
ETC [ ETC ]
