VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
10.9 SPI Peripherals
Vs1005 has two SPI (serial-to-paralle) peripherals which can be configured as a master or a
slave. Before SPIs can be used the vs1005 I/Os must be configured to peripheral mode:
• set I/O pins to peripheral mode : GPMODE1 register selects between spi mode or gpio
mode
• Embedded Serial Flash disabled : SYSTEMPD_SFENA bit reset when using SPI0 (also
boot device)
• Buffered SPI slave disabled : ETH_RXLEN_PMODE bit reset when using SPI1
SPI0 and SPI1 pins are mapped to GPIO1 port. To select peripheral mode the bits in GPMODE
register must be set HIGH.
SPI pins and their GPMODE register
SPI id
VS1005 pin Type SPI pin GPMODE register Description
SPI0
XCS0/GPIO1[0]
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
xcs GPMODE1[0]
sclk GPMODE1[1]
miso GPMODE1[2]
mosi GPMODE1[3]
xcs GPMODE1[4]
sclk GPMODE1[5]
miso GPMODE1[6]
mosi GPMODE1[7]
Master/slave chip select
Master/slave clock
Master input / slave output
Master output / slave input
Master/slave chip select
Master/slave clock
SPI0 SCLK0/GPIO1[1]
SPI0 MISO0/GPIO1[2]
SPI0 MOSI0/GPIO1[3]
SPI1
XCS1/GPIO1[4]
SPI1 SCLK1/GPIO1[5]
SPI1 MISO1/GPIO1[6]
SPI1 MOSI1/GPIO1[7]
Master input / slave output
Master output / slave input
The SPIs are mapped in Y addresses 0xFC40 (SPI0) and 0xFC50 (SPI1).
SPI Registers, Prefix SPIx_
SPI0 address SPI1 address Type Reset Abbrev
Description
0xFC40
0xFC41
0xFC42
0xFC43
0xFC44
0xFC45
0xFC50
0xFC51
0xFC52
0xFC53
0xFC54
0xFC55
r/w
r/w
r/w
r/w
r/w
r/w
0
0
0
0
0
0
CONFIG[10:0] Configuration
CLKCONFIG
STATUS[7:0]
DATA
Clock configuration
Status
Sent / received data
FSYNC
DEFAULT
SSI Sync data in master mode
Data to send (slave) if
SPIx_ST_TXFULL=’0’
Version: 0.2, 2012-03-16
47
ETC [ ETC ]
