VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
DAC Offset Registers
Reg Type Reset Abbrev
Description
0xFEC1
0xFEC2
0xFEC3
0xFEC4
0xFEC5
r/w
r/w
r/w
r/w
r/w
0
0
0
0
0
DAOSET_CF
DAOSET_LEFT_LSB[15:12]
DAOSET_LEFT
DAOSET_RIGHT_LSB[15:12] DAC right offset bits [3:0]
DAOSET_RIGHT DAC right offset bits [19:4]
DAC offset configuration register
DAC left offset bits [3:0]
DAC left offset bits [19:4]
DAOSET_CF Bits
Name Bits Description
DAOSET_CF_URUN
DAOSET_CF_FULL
DAOSET_CF_ENA
14
13
12
Data register underrun flag
Data register full flag
Enable for DAC offset
DAOSET_CF_FS 11:0 DAC offset sample rate
DAOSET_CF_URUN is an underrun flag register. The register is set if data register was read
when the full flag was not set.
DAOSET_CF_FULL is a data status register. Flag is set when data is written to DAOSET_LEFT
and DAOSET_RIGHT registers and reset when DAC reads the register.
DAOSET_CF_ENA enables DAC offset module.
DAOSET_CF_FS is used to set DAC offset sample rate. This register defines the interval in
clock cycles where the samples are added to DAC output. When new samples are read from
data registers also an interrupt request is generated.
Sample rate can be calculated from equation:
fs = Fclk/(dacoffset_cf_fs + 1)) where
dacoffset_cf_fs can have values from 0 to 4095 (0xFFF) and Fclk is the xtal clock frequency.
E.g. value 0xFFF gives sample rate of 12.288MHz / (0xFFF+1) = 3.0 kHz.
DAC and DAC offset mixing logic uses saturation to limit samples to 20-bit signed values. The
mixed values should not exceed 75% of the full scale values or the signal to noise ration is
degraded.
10.8.3 Sample Rate Converter (SRC) Registers
Vs1005 has a programmable sample rate converter which can be used to convert DAC’s input
sample rate to an other sample rate which is higher than the original sample rate.
Version: 0.2, 2012-03-16
45