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VS1005 参数 Datasheet PDF下载

VS1005图片预览
型号: VS1005
PDF下载: 下载PDF文件 查看货源
内容描述: 此产品是芬兰VLSI刚刚研发成功的音频编解码芯片样品 [此产品是芬兰VLSI刚刚研发成功的音频编解码芯片样品]
分类和应用:
文件页数/大小: 104 页 / 1715 K
品牌: ETC [ ETC ]
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VS1005g Datasheet
10
VS1005 PERIPHERALS AND REGISTERS
10.8
Audio Interfaces
Vs1005 audio path is shown in figure 10.
Figure 10: Vs1005 audio path.
10.8.1 DAC volume control
In vs1005 the DAC’s volume level can be adjusted in -0.5dB steps.
PR
EL
IM
10.8.2 DAC Offset Registers
Version: 0.2, 2012-03-16
Reg
0xFEC0
Type
r/w
DAC Volume Registers
Reset Abbrev
Description
0 DAC_VOL DAC volume control register
DAC_VOL Bits
Name Bits Description
DAC_VOL_LADD[3:0] 15:12 Left channel +0.5dB steps
DAC_VOL_LSFT[3:0] 11:8 Left channel -6dB steps
DAC_VOL_RADD[3:0]
7:4
Right channel +0.5dB steps
DAC_VOL_RSFT[3:0]
3:0
Right channel -6dB steps
DAC_VOL_LSFT and DAC_VOL_RSFT are the coarse volume control registers. They suppress
channel volume by -6dB steps.
DAC_VOL_LADD and DAC_VOL_RADD are the fine volume control registers. They add chan-
nel volume level by +0.5dB steps. Allowed values are from 0 to 11, i.e. maximum is +5.5dB.
Values between 12-15 equal to 0dB.
In vs1005 a second audio source can be mixed to DAC output. This is done with DAC offset
registers. The sample rate is programmable.
IN
AR
44
Y