VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
10.5 DSP Clock Domain Registers
10.5.1 General Purpose Software Registers
SW_REG0, SW_REG1, SW_REG2 and SW_REG3 are software registers for user purposes.
They are zeroed in reset and do not control any logic.
Software Registers
Address Type Reset Abbrev
Description
0xFC20
0xFC21
0xFC22
0xFC23
r/w
r/w
r/w
r/w
0
0
0
0
SW_REG0 16-bit general purpose sw register
SW_REG1 16-bit general purpose sw register
SW_REG2 16-bit general purpose sw register
SW_REG3 16-bit general purpose sw register
10.5.2 Peripheral IO control
VS1005 has three general purpose IO ports. Ports 0 and 1 are 16-bits and port 2 is 14 bits.
GPIO pins can be used either in GP mode or they can have also a special peripheral function.
GPIO or peripheral function can be defined for each pin separately.
GPIO Mode Registers
Address Type Reset Abbrev
Description
0xFC30
0xFC31
0xFC32
r/w
r/w
r/w
0
0
0
GPMODE0 Mode control for gpio port 0
GPMODE1 Mode control for gpio port 1
GPMODE2 Mode control for gpio port 2
GPMODE0, GPMODE1 and GPMODE2 register are used so select current GPIO mode. By
default all vs1005 pins are at GPIO mode and all GPMODE register are reset. If a peripheral
mode is reguired the pin’s GPMODE bit must be set (’1’).
10.5.3 PLL clock control
˙
Vs1005 has two clock domains, the PLL clock domain and 12MHz clock domain. The PLL is
controlled with one register.
Clock Control Register
Address Type Reset Abbrev Description
0xFC33
r/w
0
CLK_CF PLL clock control register
Version: 0.2, 2012-03-16
37
ETC [ ETC ]
