VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
registers), the interrupt controller generates an interrupt request signal for VSDSP with the cor-
responding vector value. The bit in the origin registers is reset automatically after the interrupt
is requested.
If the source is not enabled, the processor can read the origin register state and perform any
necessary actions without using interrupt generation, i.e. polling of the interrupt sources is also
possible. The bits in the interrupt origin registers can be cleared by writing ’1’ to them.
A read from the interrupt origin register returns the register state.
A write to the interrupt origin register clears bits in the interrupt origin register. All ’1’-bits in the
written value cause the corresponding bits in the interrupt origin register to be cleared. All zero-
bits cause the corresponding bits in the interrupt origin register to keep their state. For example
writing a value 0x00ff will clear the lowest eight bits in the interrupt origin register, while leaving
the upper bits as-is.
10.4.4 Vector INT_VECTOR
The last generated vector value can be read from the vector register.
10.4.5 Enable Counter INT_ENCOUNT
The global interrupt enable/disable is used to control whether an interrupt request is sent to
the processor or not. Whenever this 3-bit counter value is non-zero, interrupt requests are
not forwarded to VSDSP. The counter is increased by one whenever the interrupt controller
generates an interrupt request for VSDSP, thus disabling further interrupts.
When read, the enable counter register returns the counter value.
Don’t write directly to INT_ENCOUNT. Use INT_GLOB_DIS and INT_GLOB_EN to manipulate
the value of this register.
10.4.6 Global Disable INT_GLOB_DIS
A write (of any value) to global disable register increases the global interrupt enable/disable
counter by one. If the counter is zero, interrupt signal generation is enabled. When the inter-
rupt arbitrator generates an interrupt request for VS_DSP core, it automatically increases the
counter. The user must write to the global enable register (once) to enable interrupts.
If an interrupt is generated in the same cycle as a write to global disable register, the interrupt
enable counter is increased by two.
10.4.7 Global Enable INT_GLOB_EN
A write (of any value) to global enable register decreases the global interrupt enable/disable
counter by one. If the counter is zero, interrupt generation is enabled.
The user must write to this register once in the end of the interrupt handler to enable further
interrupts. This should be done in assembly language.
Version: 0.2, 2012-03-16
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