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VS1005 参数 Datasheet PDF下载

VS1005图片预览
型号: VS1005
PDF下载: 下载PDF文件 查看货源
内容描述: 此产品是芬兰VLSI刚刚研发成功的音频编解码芯片样品 [此产品是芬兰VLSI刚刚研发成功的音频编解码芯片样品]
分类和应用:
文件页数/大小: 104 页 / 1715 K
品牌: ETC [ ETC ]
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VS1005g Datasheet  
10 VS1005 PERIPHERALS AND REGISTERS  
10.3 VS1005 Peripherals  
System peripherals are located in Y-address space. The peripherals that use PLL clock are  
in addresses 0xFC00 - 0xFD3F and peripherals that use xtal clock are in addresses 0xFE00 -  
0xFEDF.  
Peripheral address spaces are summarized in the following table:  
VS1005 Peripheral Addresses  
Device  
Address  
PLL clocked pheripherals  
0xFC00 - 0xFC1F  
0xFC20 - 0xFC3F  
0xFC40 - 0xFC4F  
0xFC50 - 0xFC5F  
0xFC60 - 0xFC65  
Interrupt controller  
DSP interface registers  
SPI 0  
SPI 1  
10base-t ethernet controller  
0xFC66 - 0xFC6C DSP interface for peripheral data buffer  
0xFC70 - 0xFC76 Reed-Solomon codes  
0xFC77 - 0xFC7A Nand flash interface  
0xFC7B - 0xFC7F SD card interface  
0xFC80 - 0xFC9F  
High Speed USB  
0xFCA0 - 0xFCBF 16-bit GPIO port 0  
0xFCC0 - 0xFCDF 16-bit GPIO port 1  
0xFCE0 - 0xFCFF 14-bit GPIO port 2  
0xFD00 - 0xFD1F  
S/PDIF  
XTAL clocked pheripherals  
0xFE00 - 0xFE1F  
0xFE20 - 0xFE3F  
0xFE40 - 0xFE5F  
0xFE60 - 0xFE7F  
0xFE80 - 0xFE9F  
Uart  
Watchdog  
FM and A/D interface  
I2S  
Timers  
0xFEA0 - 0xFEBF RTC interface  
0xFEC0 - 0xFEDF Control and configuration registers for 12 MHz clock  
Version: 0.2, 2012-03-16  
33  
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