VS1005g Datasheet
10 VS1005 PERIPHERALS AND REGISTERS
10.4.1 Interrupt Controller Registers
Interrupt controller has three type of registers
• Enable registers, which contain enable/disable bits for each interrupt source. Bit pairs
configure the interrupt priority and disable.
• Origin registers, which contain the source flags for each interrupt. A request from an
interrupt source sets the corresponding bit. A bit is automatically reset when a request
for the source is generated.
• Enable counter register, which contains the value of the General Interrupt Enable counter,
and two registers for increasing and decreasing the value.
Interrupt Controller Registers
Address Type Reset Abbrev
Description
0xFC00
0xFC01
0xFC02
0xFC03
0xFC04
0xFC05
0xFC06
0xFC07
0xFC08
0xFC09
r/w
r/w
r/w
r/w
r/w
r/w
r
r/w
w
w
0
0
0
0
0
0
0
0
0
0
INT_ENABLEL0
INT_ENABLEL1
INT_ENABLEH0
INT_ENABLEH1
INT_ORIGIN0
INT_ORIGIN1
INT_VECTOR[4:0]
INT_ENCOUNT[2:0] Interrupt Enable Counter
INT_GLOB_DIS[-]
INT_GLOB_EN[-]
Interrupt Enable Low 0
Interrupt Enable Low 1
Interrupt Enable High 0
Interrupt Enable High 1
Interrupt Origin 0
Interrupt Origin 1
Interrupt Vector
Interrupt Global Disable
Interrupt Global Enable
10.4.2 Enable INT_ENABLE[L/H][0/1]
Interrupt enable registers selectively masks interrupt sources. Enable registers 0 contain sources
0..15 and enable registers 1 contain sources 16..31. Each source has two enable bits: one in
the enable low and one in the enable high register. If both bits are zero, the corresponding
interrupt source is not enabled, otherwise the bits select the interrupt priority.
High Low Priority
0
0
1
1
0
1
0
1
Source disabled
Priority 1
Priority 2
Priority 3
Priorities only matter when the interrupt controller decides which interrupt to generate for the
core next. This happens whenever two interrupt sources request interrupts at the same time,
or when interrupts become enabled after an interrupt handler routine or part of code where the
interrupts have been disabled.
10.4.3 Origin INT_ORIGIN[0/1]
If an interrupt source requests an interrupt, the corresponding bit in the interrupt origin regis-
ter (ORIGIN0 or ORIGIN1) will be set to ’1’. If an interrupt source is enabled (using ENABLE
Version: 0.2, 2012-03-16
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ETC [ ETC ]
