Ver 1.3
PRELIMINARY
EAGLE
3.28.7.8 SPI Clock Select Register (SPICS) ....................................................................................................................................211
3.28.7.9 SPI Response Character Register (SPIRC).........................................................................................................................211
3.29 JPEG DECODER............................................................................................................................................................212
3.29.1 JPEG DECODER MCU WIDTH Register (JDMWIDTH) ..................................................................................215
3.29.2 JPEG DECODER MCU HEIGHT Register (JDMHEIGHT) ..............................................................................215
3.29.3 JPEG DECODER Quantization Scale Control Register (JDQSC) .....................................................................215
3.29.4 JPEG DECODER Command Control Register (JDCOMCON)..........................................................................215
3.29.5 JPEG DECODER Y DC NODE Table (JDYDCNT)............................................................................................216
3.29.6 JPEG DECODER Y DC LEAF Table (JDYDCLT) .............................................................................................216
3.29.7 JPEG DECODER Y AC NODE Table (JDYACNT).............................................................................................216
3.29.8 JPEG DECODER Y AC LEAF Table (JDYACLT) ..............................................................................................216
3.29.9 JPEG DECODER UV DC NODE Table (JDUVDCNT) .....................................................................................216
3.29.10
3.29.11
3.29.12
3.29.13
3.29.14
3.29.15
3.29.16
3.29.17
3.29.18
3.29.19
3.29.20
3.29.21
JPEG DECODER UV DC LEAF Table (JDUVDCLT) ...................................................................................216
JPEG DECODER UV AC NODE Table (JDUVACNT) ..................................................................................216
JPEG DECODER UV AC LEAF Table (JDUVACLT) ....................................................................................216
JPEG DECODER STATUS Register (JDSTAT)..............................................................................................217
JPEG DECODER IRQ STATUS Register (JDIRQSTAT)................................................................................217
JPEG DECODER Data FIFO Status Register (JDDFSTAT)..........................................................................217
JPEG DECODER Enable Register (JDENA)..................................................................................................217
JPEG DECODER FIFO Clear Register (JDFCLR)........................................................................................217
JPEG DECODER FIFO Control Register (JDFCON)....................................................................................218
JPEG DECODER WAITE CONTROL Register (JDWCON)...........................................................................218
JPEG DECODER SOFTWARE RESET Register (JDSRST) ...........................................................................218
JPEG DECODER INPUT DATA FIFO Register (JDIDF)..............................................................................218
3.30 INTERNAL MEMORY CONTROLLER...............................................................................................................................219
3.30.1 Features...............................................................................................................................................................219
3.30.2 Block diagram......................................................................................................................................................219
3.30.3 Memory Map........................................................................................................................................................219
3.31 AE32000C SYSTEM CO-PROCESSOR ............................................................................................................................220
3.31.1 General description .............................................................................................................................................220
3.31.2 System Coprocessor Register ..............................................................................................................................221
3.31.2.1 Status Register(Read Only)................................................................................................................................................221
3.31.2.2 Master Command Register.................................................................................................................................................222
3.31.2.3 Supervisor/OSI Stack Pointer Register...............................................................................................................................223
3.31.2.4 User Stack Pointer Register................................................................................................................................................223
3.31.2.5 Vector Base Register..........................................................................................................................................................223
3.31.2.6 Cache Invalidation Register ...............................................................................................................................................223
3.31.2.7 Memory Bank Register ......................................................................................................................................................223
3.31.2.8 Sub-bank Index/Configuration Register.............................................................................................................................224
3.31.2.9 TLB Index Register............................................................................................................................................................224
3.31.2.10
3.31.2.11
3.31.2.12
3.31.2.13
3.31.2.14
3.31.2.15
3.31.2.16
3.31.2.17
3.31.2.18
3.31.2.19
3.31.2.20
3.31.2.21
TLB Virtual Address Register .......................................................................................................................................225
TLB Physical Address Register .....................................................................................................................................225
Sub-bank Address Register : Indexed by SCP %R8 ......................................................................................................225
General Access Point Data Register ..............................................................................................................................226
General Access Point Index Register.............................................................................................................................226
OSI RS-232C Transmit Data Register ...........................................................................................................................226
OSI RS-232C Receive Data Register.............................................................................................................................226
OSI Index Register.........................................................................................................................................................226
OSI Data Register..........................................................................................................................................................227
OSI RS-232C Status Register ........................................................................................................................................227
OSI RS-232C Control Register......................................................................................................................................227
OSI Channel Valid Register...........................................................................................................................................228
3.32 JTAG OF EAGLE.........................................................................................................................................................229
3.32.1 Features...............................................................................................................................................................229
3.32.2 Block diagram......................................................................................................................................................229
3.32.3 Description ..........................................................................................................................................................229
3.32.3.1 JTAG Instruction................................................................................................................................................................229
3.32.3.2 Tap Controller....................................................................................................................................................................230
3.32.3.3 Boundary scan register.......................................................................................................................................................230
4
ELECTRICAL CHARACTERISTICS.......................................................................................................................235
9
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
