EAGLE
PRELIMINARY
Ver 1.3
Tables
TABLE 3-1 EAGLE MEMORY MAP (NORMAL BOOT) ............................................................................................................... 33
TABLE 3-2 EAGLE MEMORY MAP (AUTO BOOT)..................................................................................................................... 33
TABLE 3-3 EAGLE VIRTUAL MEMORY MAP ............................................................................................................................ 34
TABLE 3-4 EAGLE REGISTER OFFSET ADDRESS....................................................................................................................... 35
TABLE 3-5 EAGLE REGISTER SUMMARY.................................................................................................................................. 43
TABLE 3-6 DMA REGISTERS TABLE.......................................................................................................................................... 60
TABLE 3-7 DMA DESCRIPTOR SUMMARY.................................................................................................................................. 61
TABLE 3-8 INTERRUPT CONTROLLER REGISTERS TABLE ........................................................................................................... 70
TABLE 3-9 INTERRUPT VECTOR & PRIORITY ............................................................................................................................. 72
TABLE 3-10 CRT CONTROLLER REGISTERS TABLE ................................................................................................................... 86
TABLE 3-11 NATIONAL TV SIGNAL STANDARD ........................................................................................................................ 92
TABLE 3-12 32 BIT VIDEO DATA SERIALIZATION...................................................................................................................... 95
TABLE 3-13 REGISTERS PROGRAMMING RESOLUTION REFERENCE TABLE FOR CRTC.............................................................. 97
TABLE 3-14 RENDERING ENGINE COMMAND PACKET ............................................................................................................. 100
TABLE 3-15 FREQUENCY BY P, M, N VALUE OF SPLL............................................................................................................. 110
TABLE 3-16 SAMPLING FREQUENCY AND CODEC CLOCK......................................................................................................... 124
TABLE 3-17 SAMPLING FREQUENCY AND SERIAL BIT CLOCK .................................................................................................. 124
TABLE 3-18 TOTAL LEVEL STEPS............................................................................................................................................. 124
TABLE 3-19 PAN POT STEPS ..................................................................................................................................................... 125
TABLE 3-20 VIDEO MULTI-STANDARD.................................................................................................................................... 126
TABLE 3-21 USB HOST REGISTERS LIST ................................................................................................................................. 150
TABLE 3-22 UART LCR REGISTER SETTING AND SERIAL DATA FORMAT.............................................................................. 159
TABLE 3-23 REGISTER TABLE OF UART ................................................................................................................................. 160
TABLE 3-24 UART INTERRUPT CONTROL FUNCTION.............................................................................................................. 161
TABLE 3-25 UART BAUD RATE SETTING................................................................................................................................ 164
TABLE 3-26 SAMPLING FREQUENCY AND CODEC CLOCK....................................................................................................... 173
TABLE 3-27 SAMPLING FREQUENCY AND SERIAL BIT CLOCK ................................................................................................... 173
TABLE 3-28 ENDPOINT LIST..................................................................................................................................................... 174
TABLE 3-29 USB CORE REGISTER LIST................................................................................................................................... 174
TABLE 3-30 WATCH-DOG TIMER COUNTER SETTING.............................................................................................................. 183
TABLE 3-31 SPI PIN FUNCTIONS.............................................................................................................................................. 206
TABLE 3-32 INTERNAL MEMORY MAP..................................................................................................................................... 219
TABLE 3-33 BOUNDARY SCAN CELL INFORMATION ................................................................................................................ 234
TABLE 4-1 DC SPECIFICATIONS 3.3V I/0, 5.0V TOLERANT ..................................................................................................... 235
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
12
ETC [ ETC ]
