Ver 1.3
PRELIMINARY
EAGLE
FIGURE 3-58 SPI BLOCK DIAGRAM..........................................................................................................................................205
FIGURE 3-59 SCK PHASE AND POLARITY ................................................................................................................................207
FIGURE 3-60 TRANSFER TIMING WHEN CPHA = ‘0’ ................................................................................................................207
FIGURE 3-61 TRANSFER TIMING WHEN CPHA = ‘1’ ................................................................................................................208
FIGURE 3-62 JPEG DECODER BLOCK DIAGRAM ......................................................................................................................212
FIGURE 3-63 JPEG DECODER CORE BLOCK DIAGRAM ............................................................................................................213
FIGURE 3-64 JPEG DECODER SOFTWARE FLOW CHART ..........................................................................................................214
FIGURE 3-65 INTERNAL MEMORY CONTROLLER BLOCK DIAGRAM .........................................................................................219
FIGURE 3-66 JTAG BLOCK DIAGRAM......................................................................................................................................229
FIGURE 3-67 TAP CONTROLLER OPERATION............................................................................................................................230
11
CONFIDENTIAL
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