EAGLE
PRELIMINARY
Ver 1.3
Figures
FIGURE 2-1 TOP BLOCK DIAGRAM............................................................................................................................................. 16
FIGURE 2-2 LQFP PACKAGE DIMENSION................................................................................................................................... 17
FIGURE 2-3 CABGA PACKAGE DIMENSION .............................................................................................................................. 18
FIGURE 3-1 ROM/SRAM/IO TIMING DIAGRAM........................................................................................................................ 52
FIGURE 3-2 STRUCTURE OF DMA CONTROLLER ....................................................................................................................... 59
FIGURE 3-3 STRUCTURE OF DMA DESCRIPTOR ......................................................................................................................... 61
FIGURE 3-4 EXAMPLE OF DMA DESCRIPTOR FLOW................................................................................................................... 62
FIGURE 3-5 STRUCTURE OF INTERRUPT CONTROLLER ............................................................................................................... 70
FIGURE 3-6 INTERRUPT TRIGGER MODE DESCRIPTION .............................................................................................................. 71
FIGURE 3-7 NAND FLASH CONTROLLER BLOCK DIAGRAM...................................................................................................... 78
FIGURE 3-8 TRANSMISSION THROUGH INTERNAL MEMORY OF NAND FLASH CONTROLLER ................................................... 79
FIGURE 3-9 READ/WRITE TIMING DIAGRAM OF NAND FLASH MEMORY BY NAND FLASH CONTROLLER .............................. 80
FIGURE 3-10 AUTO BOOT MODE DIAGRAM ............................................................................................................................... 80
FIGURE 3-11 CRT CONTROLLER BLOCK DIAGRAM ................................................................................................................... 93
FIGURE 3-12 CRT FIFO CONTROL BLOCK – RGB 16 BIT(5:6:5) FORMAT OPERATION............................................................. 94
FIGURE 3-13 CRTC HORIZONTAL, VERTICAL SYNC / ACTIVE SIGNAL TIMING ......................................................................... 96
FIGURE 3-14 H.264 DECODER BLOCK DIAGRAM..................................................................................................................... 101
FIGURE 3-15 DECODED IMAGE DATA PATH............................................................................................................................. 108
FIGURE 3-16 SDC BLOCK DIAGRAM ....................................................................................................................................... 113
FIGURE 3-17 SOUND MIXER BLOCK DIAGRAM........................................................................................................................ 120
FIGURE 3-18 MSB(LEFT)-JUSTIFIED FORMAT ......................................................................................................................... 124
FIGURE 3-21 VIDEO ENCODER BLOCK DIAGRAM .................................................................................................................... 127
FIGURE 3-22 VIDEO ENCODER RELATIONSHIP BETWEEN ENCODER TIMING SIGNALS AND DATA(NTSC)............................... 128
FIGURE 3-23 VIDEO ENCODER RELATIONSHIP BETWEEN ENC_VAV AND ENC_HAV............................................................. 128
FIGURE 3-24 IN MASTER MODE OF VIDEO ENCODER, RELATIONSHIP BETWEEN ENC_VAV & ENC_VPC REG........................ 129
FIGURE 3-25 VIDEO ENCODER NTSC SYSTEM CVBS TIMING & COLOR BURST PHASE.......................................................... 130
FIGURE 3-26 VIDEO ENCODER PAL SYSTEM CVBS TIMING & COLOR BURST PHASE ............................................................ 130
FIGURE 3-27 CSC IMAGE CAPTURER BLOCK DIAGRAM .......................................................................................................... 136
FIGURE 3-28 FRAME BUFFER SWITCHING & PIPE LINE OPERATION ........................................................................................ 138
FIGURE 3-29 FRAME BUFFER ASSIGNMENT ............................................................................................................................. 138
FIGURE 3-30 OSD BLOCK DIAGRAM ....................................................................................................................................... 141
FIGURE 3-31 OSD WINDOW EXAMPLE ..................................................................................................................................... 144
FIGURE 3-32 JPEG IMAGE CAPTURER BLOCK DIAGRAM......................................................................................................... 146
FIGURE 3-33 JPEG ICE FRAME BUFFER SWITCHING & PIPE LINE OPERATION ....................................................................... 148
FIGURE 3-34 YC IMAGE CAPTURE ENGINE BLOCK DIAGRAM ................................................................................................. 151
FIGURE 3-35 YC IMAGE CAPTURER BUFFER AND SCALER BUFFER SWITCHING & PIPE LINE OPERATION............................... 152
FIGURE 3-36 YC IMAGE CAPTURE Y / C BUFFER ASSIGNMENT............................................................................................... 153
FIGURE 3-37 UART BLOCK DIAGRAM .................................................................................................................................... 156
FIGURE 3-38 UART RX/TX INTERRUPT AND DATA FLOW....................................................................................................... 157
FIGURE 3-39 KEY SCAN BLOCK DIAGRAM .............................................................................................................................. 165
FIGURE 3-40 5X5 KEY MATRIX ............................................................................................................................................... 167
FIGURE 3-41 KEY SCAN TIME DIAGRAM ................................................................................................................................. 167
FIGURE 3-42 I2S WITH ADPCM BLOCK DIAGRAM.................................................................................................................. 168
FIGURE 3-43 I2S-BUS AND MSB(LEFT)-JUSTIFIED FORMAT .................................................................................................... 173
FIGURE 3-44 PRE-SCALE BLOCK DIAGRAM ............................................................................................................................. 184
FIGURE 3-45 PWM PULSE OUTPUT.......................................................................................................................................... 185
FIGURE 3-46 CAPTURE MODE TIMING DIAGRAM..................................................................................................................... 185
FIGURE 3-47 TWI CONTROLLER BLOCK DIAGRAM ................................................................................................................. 193
FIGURE 3-48 TWI-BUS INTERFACE DATA FORMAT................................................................................................................. 194
FIGURE 3-49 DATA TRANSFER ON THE TWI-BUS .................................................................................................................... 194
FIGURE 3-50 ACK SIGNAL TRANSMISSION............................................................................................................................... 195
FIGURE 3-51 BUS ARBITRATION PROCEDURES 1...................................................................................................................... 195
FIGURE 3-52 BUS ARBITRATION PROCEDURES 2...................................................................................................................... 196
FIGURE 3-53 TWI INITIALIZATION FLOW ................................................................................................................................ 197
FIGURE 3-54 TWI MASTER TRANSMIT FLOW .......................................................................................................................... 198
FIGURE 3-55 TWI MASTER RECEIVE FLOW............................................................................................................................. 199
FIGURE 3-56 TWI SLAVE OPERATION FLOW(POLLING) .......................................................................................................... 200
FIGURE 3-57 TWI SLAVE OPERATION FLOW(INTERRUPT)....................................................................................................... 201
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
10
ETC [ ETC ]
