EAGLE
PRELIMINARY
Ver 1.3
0
R/W
Number of Refresh Cycle / Period
< Refresh Source : 1MHz >
0 : 1 Cycle 1 : 2 Cycle
1b
< Register Description >
(1) Bit[11:8] : This field determines the latency in SDRAM Feedback Clock when data is read from SDRAM.
(2) Bit[1] : This bit determines the refresh period when refresh source is 1 MHz unit clock, as determined by bit[3]..
(3) Bit[0] : This bit determines the number of refresh cycles in one period or per horizontal synchronization.
3.3.7 Texture Memory Area Start Address (TMASA)
Address : FFE0 0438h
Bit
31 : 20
19:0
R/W
R/W
R
Description
Texture Memory Area Start Address
Reserved
Default Value
000h
-
Note:
This register should be configured when Non-Texture Memory mode is set up in the graphic engine (a separate Texture
Memory is not used and the Texture Memory Region is allocated in the Main Memory Region ).
If a separate Texture Memory is used (where the state bit of Non-Texture Memory mode in graphic engine has a ‘0’ value),
it is not necessary to set up the above register and the Texture Memory Start address will be automatically set to the Bank 7
region.
If part of the Local Memory is used as Texture Region, that part of memory should be prohibited from caching ( Non-
Cachable region).
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CONFIDENTIAL
58
ETC [ ETC ]
