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PKM32AG-Q 参数 Datasheet PDF下载

PKM32AG-Q图片预览
型号: PKM32AG-Q
PDF下载: 下载PDF文件 查看货源
内容描述: EAGLE是一款多媒体处理器.EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。 [EAGLE是一款多媒体处理器。EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。]
分类和应用: 解码器编码器控制器
文件页数/大小: 235 页 / 4257 K
品牌: ETC [ ETC ]
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Ver 1.3  
PRELIMINARY  
EAGLE  
GDMA Descriptor Table  
The descriptor includes the information required by DMA controller for data transfer. User should program the descriptor for  
each block that needs to be transferred. The programmed descriptors must be connected to each other. After storing the  
location of the first descriptor into GDMADT, the DMA controller shall fetch the first programmed descriptor when an  
execution command is received. After reading the descriptor, the DMA controller performs data transfer based on the  
information found inside the descriptor. The fetch and execution process is repeated after the completion of the last  
descriptor. Table 3-7 summarizes the descriptor configuration.  
Descriptor field  
Description  
This field defines the source address needed for DMA transfer. After the DMA controller  
reads the descriptor from memory, the value in this field is stored in GDMAS.  
This field defines the destination address needed for DMA transfer. After the DMA  
controller reads the descriptor from memory, the value in this field is stored in GDMAD.  
DMA transfer count. After DMA controller reads the descriptor from memory, the value  
of this field is stored in GDMAT.  
Source address  
Destination address  
count  
This field defines the start address of the next descriptor in memory. After the DMA  
controller reads the descriptor from memory, the value of this field is stored in Next  
Descriptor Address Buffer located inside the DMA controller.  
This field defines the control status of DMA transfer. After the DMA controller reads the  
descriptor from memory, the configuration setting in this field is stored in GDMACON  
and in temporary flag buffer.  
Next Description address  
Control flag  
Table 3-7 DMA Descriptor summary  
offset  
31  
0
0x0  
0x4  
source address  
Reserved  
0x8  
Destination address  
Reserved  
0xc  
0x10  
0x14  
0x18  
0x1c  
Count  
Next description address  
Reserved  
Control flag  
Figure 3-3 Structure of DMA Descriptor  
61  
CONFIDENTIAL  
Beijing Peak Microtech Co.Ltd.  
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