Ver 1.3
PRELIMINARY
EAGLE
3.4 General DMA
This is a general purpose DMA controller which supports burst data transfer from memory or IO.
There are two DMA channels. Five request sources can be selected for each channel.
Each DMA channel is equipped with a 16 x 4-byte FIFO. For a 32-bit transmission, no burst or 4/8/16 burst mode is
supported.
An interrupt signal is generated when the DMA Controller completes a transfer or an error is detected.
Figure 3-2 Structure of DMA Controller
GDMA Feature
Two-channel DMA
32-bit address control for 4-GByte Region
24-bit counter which enables a maximum of 16-MByte transfer at a time
Four external DMA request inputs
DMA request by software
Chain mode to support Scattering/Gathering for unlimited data blocks
Direct mode support which enables direct configuration
No burst or 4,8,16-bit burst transfer using 16x4-byte FIFO
Supports fix, increment, and decrement address
Interrupt state flag for interrupt polling
Data size controller to enable byte unit access
59
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
