Ver 1.3
PRELIMINARY
EAGLE
3.19.8 UART Channel 0~3 Line Status Register (ULSTAT0 ~ ULSTAT3)
Address : FFE0 8014h / FFE0 8034h / FFE0 8054h / FFE0 8074h
Bit
31 : 8
7
R/W
R
R
Description
Default Value
Reserved.
Error in RCVR FIFO(EIRF)
-
0b
: This bit is set to ‘1’ when any error occurs in receive FIFO.
6
R
Transmitter Empty(TEMT)
1b
: This bit is asserted to ‘1’ when transmit FIFO is empty. In the case
where FIFO is not used, this bit is asserted when THR and TSR are
empty.
5
4
R
R
Transmitter Holding Register Empty(THRE)
: This bit is set to ‘1’ when THR is empty.
Break Interrupt(BI)
1b
0b
: This bit is set to ‘1’ when the entire receiving data which includes start
bit , stop bit, is 0
Frame Error : This bit is set to ‘1’ when frame error occurs. It is cleared
when USTATn register is read.
3
2
1
0
R
R
R
R
0b
0b
0b
0b
0 : No Error
1 : Error
Parity Error : This bit is set to ‘1’ when parity error occurs. It is cleared
when USTATn register is read.
0 : No Error
1 : Error
Overrun Error : This bit is set to ‘1’ when overrun error occurs. It is
cleared when USTATn register is read.
0 : No Error
1 : Error
Receive FIFO Data Ready : This bit is set to ‘1’ if Rx FIFO has data,
otherwise it is set to ‘0’
0 : Rx FIFO is empty.
1 : Rx FIFO has some data.
3.19.9 UART Channel 0~3 Divisor Latch LSB Register (UDLL0 ~ UDLL3)
Address : FFE0 8000h / FFE0 8020h / FFE0 8040h / FFE0 8060h
Bit
31: 8
7 : 0
R/W
R
R/W
Description
Reserved.
Divisor Latch Least Significant Byte
Default Value
-
00h
Access to this register is only allowed when LCR[7] is set to ‘1’
3.19.10 UART Channel 0~3 Divisor Latch MSB Register (UDLM0 ~ UDLM3)
Address : FFE0 8004h / FFE0 8024h / FFE0 8044h / FFE0 8064h
Bit
31: 8
7 : 0
R/W
R
R/W
Description
Reserved.
Divisor Latch Most Significant Byte
Default Value
-
00h
Access to this register is only allowed when LCR[7] is set to ‘1’
The following equation is to calculate the Tx/Rx Baud Rate:
163
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
