EAGLE
PRELIMINARY
Ver 1.3
Summary of Registers
00
DLAB = 0
RX
Buffer
Register
URB
00
DLAB = 0
TX
Holding
Register
UTH
04
00
04
Bit
No
08
08
0C
14
DLAB = 0
Interrupt
Enable
Register
UIE
DLAB = 1 DLAB = 1
Interrupt
Ident.
Register
UII
FIFO
Control
Register
UFCON
R/W
Line
Control
Register
ULCON
R/W
Line
Status
Register
ULSTAT
R
Divisor
Latch
(LS)
Divisor
Latch
(MS)
UDLL
R/W
UDLM
R/W
R
W
R/W
R
Enable
Received
Data
Available
Interrupt
Enable TX
Holding
Register
Empty
Word
Length
Select
Bit 0
‘0’ if
Interrupt
Pending
FIFO
Enable
Data
Ready
0
1
Data Bit 0
Data Bit 1
Data Bit 0
Data Bit 1
Bit 0
Bit 1
Bit 0
Bit 1
Word
Length
Select
Bit 1
RCVR
FIFO
Reset
Interrupt
ID Bit 0
Overrun
Error
Interrupt
Enable RX
XMIT
FIFO
Reset
Number of
Stop
Interrupt
ID Bit 1
Parity
Error
2
3
4
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 2 Line Status
Interrupt
Bit 2
Bit 3
Bit 4
Bit 2
Bit 3
Bit 4
Bits
Interrupt
ID Bit 2
Parity
Enable
Even
Parity
Select
Framing
Error
Data Bit 3
0
0
Break
Interrupt
Data Bit 4
0
0
0
Reserved
TX
Holding
Register
Stick
Parity
5
6
7
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 5
Data Bit 6
Data Bit 7
0
0
0
Reserved
Bit 5
Bit 6
Bit 7
Bit 5
Bit 6
Bit 7
RCVR
Trigger(LS
B)
FIFO
Enabled
Set
Break
TX
Empty
RCVR
Trigger(M
SB)
Divisor
Latch
Access Bit
Error in
RCVR
FIFO
FIFO
Enabled
* ULCON[7](Divisor Latch Access Bit) = DLAB
* FIFO Control Register : (DLAB = 0) Register Write, (DLAB = 1) Register Read
* Address 10(30), 18(38), 1C(3C)is skipped because of 16550 UART compatibility
Table 3-23 Register Table of UART
3.19.2 UART Channel 0~3 Receiver Buffer Register (URB0 ~ URB3)
Address : FFE0 8000h / FFE0 8020h / FFE0 8040h / FFE0 8060h
Bit
31: 8
7 : 0
R/W
R
R
Description
Default Value
Reserved.
Receive Data for UART0 ~3
-
00h
3.19.3 UART Channel 0~3 Transmitter Holding Register (UTH0 ~ UTH3)
Address : FFE0 8000h / FFE0 8020h / FFE0 8040h / FFE0 8060h
Bit
31: 8
7 : 0
R/W
W
W
Description
Default Value
Reserved.
Transmit Data for UART0 ~ 3
-
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
160
ETC [ ETC ]
