Ver 1.3
PRELIMINARY
EAGLE
3.10
PLL & Power Manager
3.10.1 System Clock Source Select Register (SPLLCKSEL)
Address : FFE0 2000h
Bit
31 : 1
0
R/W
R
R/W
Description
Default Value
Reserved
Clock Source Select
-
0b
0 : Slow clock (use clock divided by SPLLCON bit[2:0])
1 : SPLL clock
3.10.2 System PLL Control Register (SPLLCON)
Address : FFE0 2004h
Bit
31 : 9
8
R/W
R
R/W
Description
Default Value
Reserved
-
0b
Write Protect PLL Program Register (SPLLPMN)
0 : Write Disable.
1 : Write Enable.
7
6 : 5
4
R
R/W
R/W
Reserved.
SPLL Test Mode
Power Down Mode for SPLL
0 : SPLL Enable
-
0h
0b
1 : SPLL Disable (Power Down)
3
R
Reserved.
-
2 : 0
R/W
Divider Value for Slow Clock
Slow Clock = Xin / (2 this_value ), Max Value : 6
When external clock is used instead of the PLL output, this register
provides the divider value for slow mode (SPLLCON bit[4] = 1).
000b
109
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.