DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
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Controlled output edge rates in 100Mbps
Supports a 10Base-T interface without the need for
an external filter
Provides Loop-back mode for system diagnostics
Includes Flexible LED configuration capability
Digital clock recovery circuit using advanceddigital
algorithm to reduce jitter
Low-power, high-performance CMOS process
Available in both a 100 pin LQFP and a 100 QFP
package
Features
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10/100Base-TX physical-layer, single-chip transceiver
Compliant with IEEE 802.3u 100Base-TX standard
Compliant with ANSI X3T12 TP-PMD 1995 standard
Compliant with IEEE 802.3u Auto-negotiation protocol
for automatic link type selection
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Supports the MII with serial management interface
Supports Full Duplex operation for 10 and 100Mbps
High performance 100Mbps clock generator and data
recovery circuitry
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Adaptive equalization circuitry for 100Mbps receiver
Pin Configuration: DM9101E LQFP
N C
N C
1
COL
75
74
73
72
71
70
69
68
67
66
65
64
63
2
C R S
RX_CLK
N C
3
A G N D
AVCC
AVCC
RXI-
4
D V C C
D G N D
RXD0
5
6
7
RXD1
RXI+
RXD2
8
A G N D
A G N D
10TXO-
10TXO+
AVCC
AVCC
A G N D
A G N D
N C
9
RXD3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
D V C C
D G N D
MDIO
M D C
DM9101E
TX_CLK
TX_EN
D V C C
D G N D
TXD0
62
6
1
60
59
58
57
56
N C
AVCC
AVCC
A G N D
A G N D
100TXO-
100TXO+
AVCC
TXD1
TXD2
TXD3
55
54
TX_ER/TXD4
TXLED#
RXLED#
LINKLED#
53
52
5
1
Final
3
Version: DM9101-DS-F03
July 22, 1999
ETC [ ETC ]
