ST72104G, ST72215G, ST72216G, ST72254G
POWER SAVING MODES (Cont’d)
9.4 HALT MODE
Figure 20. HALT Mode Flow-chart
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
ST7 HALT instruction (see Figure 20).
HALT INSTRUCTION
ENABLE
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 5, “Interrupt
Mapping,” on page 26) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 19).
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
WATCHDOG
0
DISABLE
WDGHALT 1)
1
WATCHDOG
RESET
OSCILLATOR
OFF
PERIPHERALS 2)
OFF
OFF
0
CPU
I BIT
N
RESET
In the HALT mode the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
Y
N
INTERRUPT 3)
OSCILLATOR
PERIPHERALS
CPU
Y
ON
OFF
ON
1
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 16.1 "OPTION BYTES" on page 133 for
more details).
I BIT
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
ON
ON
ON
X 4)
Figure 19. HALT Mode Timing Overview
I BIT
4096 CPU CYCLE
RUN
HALT
RUN
DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
HALT
INSTRUCTION
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
RESET
OR
INTERRUPT
FETCH
VECTOR
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 5, “Interrupt Mapping,” on page 26 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
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ETC [ ETC ]
