ST72104G, ST72215G, ST72216G, ST72254G
INTERRUPTS (Cont’d)
Figure 15. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
N
Y
INTERRUPT
PENDING?
Y
FETCH NEXT INSTRUCTION
N
IRET?
STACK PC, X, A, CC
SET I BIT
Y
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 5. Interrupt Mapping
Exit
from
HALT
Source
Block
Register Priority
Address
Vector
N°
Description
Label
Order
RESET
TRAP
ei0
Reset
yes
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
Highest
Priority
Software Interrupt
N/A
1
0
1
External Interrupt Port A7..0 (C5..0 )
yes
1
ei1
External Interrupt Port B7..0 (C5..0 )
2
CSS
Clock Security System Interrupt
SPI Peripheral Interrupts
TIMER A Peripheral Interrupts
Not used
CRSR
SPISR
TASR
3
SPI
no
4
TIMER A
5
6
TIMER B
TIMER B Peripheral Interrupts
Not used
TBSR
no
7
8
Not used
9
Not used
10
11
12
13
Note
Not used
I²C
I²C Peripheral Interrupt
Not Used
I2CSRx
no
Lowest
Priority
Not Used
1. Configurable by option byte.
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ETC [ ETC ]
