ST72104G, ST72215G, ST72216G, ST72254G
7.4 CLOCK SECURITY SYSTEM (CSS)
The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the in-
tegration of the security features in the applica-
tions, it is based on a clock filter control and an In-
ternal safe oscillator. The CSS can be enabled or
disabled by option byte.
Limitation detection
The automatic safe oscillator selection is notified
by hardware setting the CSSD bit of the CRSR
register. An interrupt can be generated if the CS-
SIE bit has been previously set.
These two bits are described in the CRSR register
description.
7.4.1 Clock Filter Control
7.4.3 Low Power Modes
The clock filter is based on a clock frequency limi-
tation function.
Mode
WAIT
Description
This filter function is able to detect and filter high
frequency spikes on the ST7 main clock.
No effect on CSS. CSS interrupt cause the
device to exit from Wait mode.
If the oscillator is not working properly (e.g. work-
ing at a harmonic frequency of the resonator), the
current active oscillator clock can be totally fil-
tered, and then no clock signal is available for the
ST7 from this oscillator anymore. If the original
clock source recovers, the filtering is stopped au-
tomatically and the oscillator supplies the ST7
clock.
The CRSR register is frozen. The CSS (in-
cluding the safe oscillator) is disabled until
HALT mode is exited. The previous CSS
configuration resumes when the MCU is
woken up by an interrupt with “exit from
HALT mode” capability or from the counter
reset value when the MCU is woken up by a
RESET.
HALT
7.4.2 Safe Oscillator Control
7.4.4 Interrupts
The safe oscillator of the CSS block is a low fre-
quency back-up clock source (see Figure 13).
The CSS interrupt event generates an interrupt if
the corresponding Enable Control Bit (CSSIE) is
set and the interrupt mask in the CC register is re-
set (RIM instruction).
If the clock signal disappears (due to a broken or
disconnected resonator...) during a safe oscillator
period, the safe oscillator delivers a low frequency
clock signal which allows the ST7 to perform some
rescue operations.
Enable Exit
Control from
Exit
Event
Flag
Interrupt Event
from
1)
Bit
Wait Halt
Automatically, the ST7 clock source switches back
from the safe oscillator if the original clock source
recovers.
CSS event detection
(safe oscillator acti- CSSD CSSIE
vated as main clock)
Yes No
Note 1: This interrupt allows to exit from active-halt
mode if this mode is available in the MCU.
Figure 13. Clock Filter Function and Safe Oscillator Function
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CPU
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OSC
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SFOSC
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ETC [ ETC ]
