ST72104G, ST72215G, ST72216G, ST72254G
7.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR)
Read/Write
Bit 1 = CSSD Clock security system detection
This bit indicates that the safe oscillator of the
clock security system block has been selected by
hardware due to a disturbance on the main clock
Reset Value: 000x 000x (XXh)
7
0
signal (f
). It is set by hardware and cleared by
OSC
reading the CRSR register when the original oscil-
LVD
RF
CSS CSS WDG
0
0
0
0
lator recovers.
IE
D
RF
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by option byte, the
CSSD bit value is forced to 0.
Bit 7:5 = Reserved, always read as 0.
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last RESET was gener-
ated by the LVD block. It is set by hardware (LVD
reset) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by option byte, the LVDRF bit
value is undefined.
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last RESET was gener-
ated by the watchdog peripheral. It is set by hard-
ware (Watchdog RESET) and cleared by software
(writing zero) or an LVD RESET (to ensure a sta-
ble cleared state of the WDGRF flag when the
CPU starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 3 = Reserved, always read as 0.
RESET Sources
External RESET pin
LVDRF WDGRF
Bit 2 = CSSIE Clock security syst interrupt enable
.
0
0
1
0
1
X
This bit enables the interrupt when a disturbance
is detected by the clock security system (CSSD bit
set). It is set and cleared by software.
Watchdog
LVD
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
Refer to Table 5, “Interrupt Mapping,” on page 26
for more details on the CSS interrupt vector. When
the CSS is disabled by option byte, the CSSIE bit
has no effect.
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
Table 4. Clock, Reset and Supply Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
CRSR
Reset Value
LVDRF
x
CSSIE
0
CSSD
0
WDGRF
x
0025h
0
0
0
0
23/140
ETC [ ETC ]
