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TMXF281553BAL-3C-DB 参数 Datasheet PDF下载

TMXF281553BAL-3C-DB图片预览
型号: TMXF281553BAL-3C-DB
PDF下载: 下载PDF文件 查看货源
内容描述: 电信/数据通信\n [Telecomm/Datacomm ]
分类和应用: 电信数据通信
文件页数/大小: 784 页 / 10078 K
品牌: ETC [ ETC ]
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TMXF28155 Supermapper  
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1  
Data Sheet  
June 2002  
12 28-Channel Framer Registers (continued)  
Table 450. FRM_HCR6, Transmit HDLC Channel Register 6 (WO)  
Address* Bit  
Name  
Function  
Reset  
Default  
Reserved. Must write to 0.  
0x8HP85 15:10  
9:8  
RSVD  
0x00  
00  
FRM_HTFUNC[1:0]  
Transmit Data Function. These two bits indicate the  
action to be taken by writing this register:  
00 = add DATA to the Tx FIFO (non-EOP).  
01 = add DATA to the Tx FIFO as EOP data (i.e., last byte of  
packet).  
10 = abort last incomplete data packet in FIFO. (If written after  
an EOP byte, this may abort the previous packet.)  
11 = reserved.  
7:0  
FRM_HTDATA[7:0]  
Transmit Data Register. When FRM_HTFUNC[1:0] = 00  
or 01, then these bits contain a byte of data to be written to  
the FIFO.  
0x00  
* See Table 444 on page 309 for mapping of H and P.  
Table 451. FRM_HCR7, Transmit HDLC Channel Register 7 (RO)  
Address* Bit  
0x8HP86 15:10  
9:0  
Name  
Function  
Reserved. Must write to 0.  
Reset Default  
RSVD  
0x0  
FRM_HTCOUNT[9:0] Transmit FIFO Byte Count. These bits indicate  
the number of bytes available to be filled in the Tx  
FIFO for the specific channel.  
x80 (x200 in  
large buffer  
mode)  
* See Table 444 on page 309 for mapping of H and P.  
Table 452. FRM_HCR8, Receive HDLC Channel Register 8 (R/W)  
Address* Bit  
Name  
Function  
Reset  
Default  
Reserved. Must write to 0.  
0x8HP00 15:13  
RSVD  
000  
12:8 FRM_RTIMESLOT[4:0] Received HDLC Time Slot. These bits indicate (in  
00000  
binary) the time-slot number assigned to this channel.  
7:0  
FRM_RBIT_IM[7:0]  
Received HDLC Bit Assignment. These bits indicate  
which bits of a time slot are to be assigned to this channel  
(1 = bit assigned).  
0x00  
* See Table 444 on page 309 for mapping of H and P.  
Table 453. FRM_HCR9, Receive HDLC Channel Register 9 (R/W)  
Address* Bit  
Name  
Function  
Reset  
Default  
0x8HP01 15:14  
FRM_RFRAME_  
SEL[1:0]  
Receive HDLC Frame Select. These bits are encoded to  
select odd and/or even numbered frames assigned to this  
channel.  
000  
00 = no data selected. (Use for loopback mode.)  
01 = data from even frames selected (Fs, FAS).  
10 = data from odd frames selected (FT, NOTFAS, ESF-DL).  
11 = data from all (even and odd) frames selected.  
Reserved. Must write to 0.  
13:5  
4:0  
RSVD  
0x0  
FRM_RLINK[4:0] Receive HDLC Link Select. These bits indicate (in binary)  
00000  
the link number assigned to this channel.  
* See Table 444 on page 309 for mapping of H and P.  
312  
Agere Systems Inc.  
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